On 05/13/2014 05:21 AM, Tony Lindgren wrote:
* Paul E. McKenney paul...@linux.vnet.ibm.com [140505 11:11]:
On Mon, May 05, 2014 at 05:39:43PM +0800, Alex Shi wrote:
I keep seeing the RCU stall problem on panda board from 3.10 kernel to
latest upstream kernel
and google find some one report
Get the two interrupt line number at the same time by merging the two
instance of if(node){}else{} places.
replace the pdev-dev with the already existing dev which makes it possible
to collapse lines with devm_request_irq()
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
Hi,
We are requesting redundant information via DT for the driver since the very
same
data is available in the HW: by reading and decoding the content of CCCFG
register we can get:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git
From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git
From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE
The ti,edma-regions; ti,edma-slots and dma-channels in DT are
redundant
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 65 +++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
Adding device tree entry for CPSW to make it work in Dual EMAC mode.
DRA7 cpsw phy sel driver patch has been pulled in net-next git with the
following commit id *d415fa1b88748d664b7b6a310dd8e699d2686cf7*
Mugunthan V N (3):
pinctrl: dra7: dt-bindings: add pin off modes for dra7 SoC
arm/dts:
Add CPSW and MDIO related device tree data for DRA7XX and made as status
disabled. Phy-id, pinmux for active and sleep state needs to be added in
board dts files and enable the CPSW device.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 59
Add pin off modes for dra7 SoC so that during module disable or suspend
state it can help saving power
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
include/dt-bindings/pinctrl/dra.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/pinctrl/dra.h
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 103 +
1 file changed, 103 insertions(+)
diff
On 05/13/2014 01:07 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [140512 14:41]:
On Sunday 11 May 2014 11:55 AM, Tony Lindgren wrote:
* Kevin Hilman khil...@linaro.org [140509 16:46]:
Roger Quadros rog...@ti.com writes:
Kevin,
On 05/09/2014 01:15 AM, Kevin Hilman
On Tuesday 13 May 2014 01:13 PM, Peter Ujfalusi wrote:
Hi,
We are requesting redundant information via DT for the driver since the very
same
data is available in the HW: by reading and decoding the content of CCCFG
register we can get:
Number of channels: NUM_DMACH
Number of regions:
Find whether we are running on newer silicon. The babble control
register reads 0x4 by default in newer silicon as opposed to 0
in old versions of AM335x. Based on this enable the sw babble
control logic.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/musb/musb_dsps.c | 34
For DSPS platform usb_phy_vbus(_off/_on) are NOPs.
So during musb_platform_reset() call usb_phy(_shutdown/_init)
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/musb/musb_dsps.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
Series add support for SW babble control logic found in
new silicon versions of AM335x. Runtime differentiation of
silicon version is done by checking the BABBLE_CTL register.
For newer silicon the register default value read is 0x4 and
for older versions its 0x0.
Patch 1 - Convert recover work
Currently musb_platform_reset() is only used by dsps.
In case of BABBLE interrupt for other platforms the musb_platform_reset()
is a NOP. In such situations no need to re-initialize the endpoints.
Also in the latest silicon revision of AM335x, we do have a babble recovery
mechanism without
During babble condition both first disconnect of devices are
initiated. Make sure MUSB controller is reset and re-initialized
after all disconnects.
To acheive this schedule a delayed work for babble rrecovery.
While at that convert udelay to usleep_range.
Refer
Add AM437x GP EVM cpsw device tree node
Mugunthan V N (2):
ARM: dts: am4372: Add cpsw phy sel dt node
ARM: dts: am437x-gp-evm: Add ethernet support for GP EVM
arch/arm/boot/dts/am4372.dtsi | 6
arch/arm/boot/dts/am437x-gp-evm.dts | 72 +
2
Add cpsw phy sel device tree node for selecting phy mode in control module
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index
Add CPSW ethernet support for AM437x GP EVM which has one slave pinned out
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 72 +
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
Tony/Benoit
On Tuesday 13 May 2014 01:34 PM, Mugunthan V N wrote:
Adding device tree entry for CPSW to make it work in Dual EMAC mode.
DRA7 cpsw phy sel driver patch has been pulled in net-next git with the
following commit id *d415fa1b88748d664b7b6a310dd8e699d2686cf7*
Mugunthan V N (3):
On Thu, May 8, 2014 at 9:06 AM, Rajendra Nayak rna...@ti.com wrote:
Do you mind picking this fix up via the GPIO tree?
Yes, it's merged to my devel branch now with the ACKs.
Alternatively you could
Ack this if you are fine and we can take both Patch 1/2 and Patch 2/2 from
this
series via
Hi George,
On 05/13/2014 10:31 AM, George Cherian wrote:
Series add support for SW babble control logic found in
new silicon versions of AM335x. Runtime differentiation of
silicon version is done by checking the BABBLE_CTL register.
For newer silicon the register default value read is 0x4
On 05/13/2014 11:33 AM, Sekhar Nori wrote:
On Tuesday 13 May 2014 01:13 PM, Peter Ujfalusi wrote:
Hi,
We are requesting redundant information via DT for the driver since the very
same
data is available in the HW: by reading and decoding the content of CCCFG
register we can get:
Number of
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git
From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE
The ti,edma-regions; ti,edma-slots and dma-channels in DT are
redundant
From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
dma-channels, ti,edma-regions and ti,edma-slots no longer needed in DT since
the the same information is available in the IP's CCCFG register.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git
The pdata has been just allocated with devm_kzalloc() in
edma_setup_info_from_dt() and passed to this function.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
arch/arm/common/edma.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
Hi,
Changes sicne v1:
- added missing patch to remove the memset from edma_of_parse_dt()
We are requesting redundant information via DT for the driver since the very
same
data is available in the HW: by reading and decoding the content of CCCFG
register we can get:
Number of channels: NUM_DMACH
On 12/05/14 18:51, Tony Lindgren wrote:
It's already in v3.15.
Oh great.. And you dumped it into arch/arm/mach-omap2 too and I somehow
even acked it :( Looks like there's also the custom mux hacks. And
custom hwmod hacks. And ongoing soc_is_xxx tinkering. Now let's not add
The
On Tue, May 13, 2014 at 12:51 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
On 12/05/14 18:51, Tony Lindgren wrote:
It's already in v3.15.
Oh great.. And you dumped it into arch/arm/mach-omap2 too and I somehow
even acked it :( Looks like there's also the custom mux hacks. And
custom
On 5/13/2014 3:16 PM, Daniel Mack wrote:
Hi George,
On 05/13/2014 10:31 AM, George Cherian wrote:
Series add support for SW babble control logic found in
new silicon versions of AM335x. Runtime differentiation of
silicon version is done by checking the BABBLE_CTL register.
For newer silicon
On 05/13/2014 01:57 PM, George Cherian wrote:
On 5/13/2014 3:16 PM, Daniel Mack wrote:
On 05/13/2014 10:31 AM, George Cherian wrote:
Series add support for SW babble control logic found in
new silicon versions of AM335x. Runtime differentiation of
silicon version is done by checking the
Hi Arnd,
On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote:
On Thursday 08 May 2014 18:05:11 Jingoo Han wrote:
On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote:
On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote:
In DRA7, the cpu sees 32bit address, but the pcie controller
On Tuesday 13 May 2014 18:01:59 Kishon Vijay Abraham I wrote:
On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote:
On Thursday 08 May 2014 18:05:11 Jingoo Han wrote:
On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote:
On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote:
In
On 05/12/2014 04:57 PM, Robert Nelson wrote:
Either case if fine with me. As who knows when the dtc overlay will
every truly make it mainline, as the capemgr was the only real kernel
user of the i2c/at24 eeprom information.
Sounds like we should keep it disabled though so u-boot can be used
On 5/13/2014 5:50 PM, Daniel Mack wrote:
On 05/13/2014 01:57 PM, George Cherian wrote:
On 5/13/2014 3:16 PM, Daniel Mack wrote:
On 05/13/2014 10:31 AM, George Cherian wrote:
Series add support for SW babble control logic found in
new silicon versions of AM335x. Runtime differentiation of
Hi George,
On 05/13/2014 02:57 PM, George Cherian wrote:
I never enabled the MUSB_BABBLE_SW_SESSION_CTRL in the MUSB_BABBLE_CTL reg.
can you try with the following patch.
diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c
index 1ae6681..1160cd1 100644
---
Hi Daniel,
On 5/13/2014 6:44 PM, Daniel Mack wrote:
Hi George,
On 05/13/2014 02:57 PM, George Cherian wrote:
I never enabled the MUSB_BABBLE_SW_SESSION_CTRL in the MUSB_BABBLE_CTL reg.
can you try with the following patch.
diff --git a/drivers/usb/musb/musb_dsps.c
Hi Arnd,
On Tuesday 13 May 2014 06:17 PM, Arnd Bergmann wrote:
On Tuesday 13 May 2014 18:01:59 Kishon Vijay Abraham I wrote:
On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote:
On Thursday 08 May 2014 18:05:11 Jingoo Han wrote:
On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote:
On
On Tuesday 13 May 2014 18:56:23 Kishon Vijay Abraham I wrote:
If you have a case where the outbound translation is a 256MB (i.e. 28bit)
section of the CPU address space, that could be represented as
ranges = 0x8200 0 0 0xb000 0 0x1000;
or
ranges =
On 05/13/2014 03:24 PM, George Cherian wrote:
Basically, there are 2 types of babble conditions.
1) Transient babble condition - which could be recovered from without an
IP reset .
2) Babble condition - which could be recovered from only by doing an IP
reset.
Ok, thanks for the
On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote:
On Tuesday 13 May 2014 18:56:23 Kishon Vijay Abraham I wrote:
If you have a case where the outbound translation is a 256MB (i.e. 28bit)
section of the CPU address space, that could be represented as
ranges = 0x8200 0 0
Hi Balbi,
Do you have any comment for this patch?
Thanks
Jincan
On Wed, May 07, 2014 at 05:53:44PM -0400, Zhuang Jin Can wrote:
A delayed status request may be queued before composite framework returns
USB_GADGET_DELAYED_STATUS, because the thread queueing the request can run
on a different
On Tue, May 13, 2014 at 2:53 PM, Tom Rini tr...@ti.com wrote:
On 05/12/2014 04:57 PM, Robert Nelson wrote:
Either case if fine with me. As who knows when the dtc overlay will
every truly make it mainline, as the capemgr was the only real kernel
user of the i2c/at24 eeprom information.
On 05/13/2014 10:06 AM, Javier Martinez Canillas wrote:
Agreed. I think that until the device tree overlay and the cape
manager find their way into mainline we should treat capes as if they
were expansion boards attached to a Computer-on-Module. That is, a
static based board which its own DTS
On Tuesday 13 May 2014 04:10 AM, Roger Quadros wrote:
On 05/13/2014 01:07 AM, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [140512 14:41]:
On Sunday 11 May 2014 11:55 AM, Tony Lindgren wrote:
* Kevin Hilman khil...@linaro.org [140509 16:46]:
Roger Quadros rog...@ti.com
On Tue, May 13, 2014 at 04:06:02PM +0200, Javier Martinez Canillas wrote:
On Tue, May 13, 2014 at 2:53 PM, Tom Rini tr...@ti.com wrote:
On 05/12/2014 04:57 PM, Robert Nelson wrote:
Either case if fine with me. As who knows when the dtc overlay will
every truly make it mainline, as the
On Tue, May 13, 2014 at 4:22 PM, Matt Porter matt.por...@linaro.org wrote:
On Tue, May 13, 2014 at 04:06:02PM +0200, Javier Martinez Canillas wrote:
On Tue, May 13, 2014 at 2:53 PM, Tom Rini tr...@ti.com wrote:
On 05/12/2014 04:57 PM, Robert Nelson wrote:
Either case if fine with me. As who
On OMAP4 panda board, there have been several bug reports about boot
hang and lock-ups with CPU_IDLE enabled. The root cause of the issue
is missing interrupts while in idle state. Commit cb7094e8 {cpuidle / omap4 :
use CPUIDLE_FLAG_TIMER_STOP flag} moved the broadcast notifiers to common
code for
Hi,
On Tue, May 13, 2014 at 09:45:51PM -0400, Zhuang Jin Can wrote:
Hi Balbi,
Do you have any comment for this patch?
do you have an easy test-case which I can use to validate on my end ?
--
balbi
signature.asc
Description: Digital signature
* Javier Martinez Canillas jav...@dowhile0.org [140513 04:40]:
On Tue, May 13, 2014 at 12:51 PM, Tomi Valkeinen tomi.valkei...@ti.com
wrote:
On 12/05/14 18:51, Tony Lindgren wrote:
It's already in v3.15.
Oh great.. And you dumped it into arch/arm/mach-omap2 too and I somehow
even
* Tomi Valkeinen tomi.valkei...@ti.com [140512 07:45]:
On 12/05/14 17:39, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [140512 04:36]:
On 09/05/14 17:37, Tony Lindgren wrote:
This is just the 3730-evm with the Sharp VGA panel mentioned in
this series.
Hmm, well, those
On Thu, May 08, 2014 at 03:52:17PM +0200, Arnd Bergmann wrote:
The isp1301-omap driver cannot be built-in if the tps65010 driver
is a module, otherwise we get a link error from the reference to
the tps65010_set_vbus_draw function.
There is already a hack in the driver to work around the
On Tue, May 13, 2014 at 10:05:34AM -0500, Felipe Balbi wrote:
Hi,
On Tue, May 13, 2014 at 09:45:51PM -0400, Zhuang Jin Can wrote:
Hi Balbi,
Do you have any comment for this patch?
do you have an easy test-case which I can use to validate on my end ?
The issue was reproduced on a
* Alex Shi alex@linaro.org [140512 23:37]:
On 05/13/2014 05:21 AM, Tony Lindgren wrote:
* Paul E. McKenney paul...@linux.vnet.ibm.com [140505 11:11]:
On Mon, May 05, 2014 at 05:39:43PM +0800, Alex Shi wrote:
I keep seeing the RCU stall problem on panda board from 3.10 kernel to
Hi,
On Thu, May 08, 2014 at 03:03:07PM +0530, George Cherian wrote:
Enabling the core interrupts in complete is too late for XHCI, and stops
xhci from proper operation. So remove prepare and complete and disable/enable
isn't this a bug in xhci ? I mean the driver should make no assumption
as
Hi,
On Thu, May 08, 2014 at 03:03:03PM +0530, George Cherian wrote:
Calculate the wrapper register offsets in a seperate function.
Improve code readability, decrease the dwc3_probe() size.
Signed-off-by: George Cherian george.cher...@ti.com
---
drivers/usb/dwc3/dwc3-omap.c | 80
* Uwe Kleine-König u.kleine-koe...@pengutronix.de [140511 23:04]:
Hi Wolfram,
On Fri, May 09, 2014 at 05:15:50PM +0200, Wolfram Sang wrote:
From: Wolfram Sang w...@sang-engineering.com
In the comments, LCD pins 16-23 were numbered in the wrong order.
Fix this and use proper pinmux
Hi Javier,
On May 13, 2014, at 7:39 AM, Javier Martinez Canillas wrote:
On Tue, May 13, 2014 at 4:22 PM, Matt Porter matt.por...@linaro.org wrote:
On Tue, May 13, 2014 at 04:06:02PM +0200, Javier Martinez Canillas wrote:
On Tue, May 13, 2014 at 2:53 PM, Tom Rini tr...@ti.com wrote:
On
* Sebastian Reichel s...@kernel.org [140508 12:55]:
Hi,
On Mon, Apr 07, 2014 at 02:28:46PM +0200, Sebastian Reichel wrote:
Add support for OMAP3 ROM Random Number Generator via
pdata-quirks.
ping
Thanks applying into omap-for-v3.16/board.
Tony
--
To unsubscribe from this list: send
* Roger Quadros rog...@ti.com [140505 02:55]:
Add USB pinmux information and USB modes
for the USB controllers.
CC: Benoît Cousson bcous...@baylibre.com
Reviewed-by: Felipe Balbi ba...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 24
* Mugunthan V N mugunthan...@ti.com [140507 02:31]:
Add CPSW ethernet support for AM437x GP EVM which has one slave pinned out
Signed-off-by: Mugunthan V N mugunthan...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 72
+
1 file changed, 72
* Pekon Gupta pe...@ti.com [140509 13:41]:
+gpmc {
+ pinctrl-names = default;
+ pinctrl-0 = nand_flash_x16;
+ ranges = 0 0 0 0x0100;/* CS0: NAND */
+ nand@0,0 {
+ reg = 0 0 0x380; /* CS0, offset=0x0, reg-map size=0x380 */
Just noticed this, can you please
* Pekon Gupta pe...@ti.com [140509 13:48]:
1) NAND device memory is not directly accessible to CPU, its indirectly
accessed
via registers. So the 'reg' property for GPMC NAND nodes should be limited
to
address range of internal GPMC registers only.
2) Also, minimum granularity of
Hello Pantelis,
On Tue, May 13, 2014 at 7:07 PM, Pantelis Antoniou
pantelis.anton...@gmail.com wrote:
Hi Javier,
On May 13, 2014, at 7:39 AM, Javier Martinez Canillas wrote:
On Tue, May 13, 2014 at 4:22 PM, Matt Porter matt.por...@linaro.org wrote:
On Tue, May 13, 2014 at 04:06:02PM +0200,
Hi,
On Tue, May 13, 2014 at 8:24 AM, George Cherian george.cher...@ti.com wrote:
Hi Daniel,
On 5/13/2014 6:44 PM, Daniel Mack wrote:
Hi George,
On 05/13/2014 02:57 PM, George Cherian wrote:
I never enabled the MUSB_BABBLE_SW_SESSION_CTRL in the MUSB_BABBLE_CTL
reg.
can you try with
On Mon, May 5, 2014 at 7:03 PM, Nishanth Menon n...@ti.com wrote:
CPUFreq usage of OPP should be independent of the ordering of type of
data storage inside OPP layer. The current operations can equally be
performed by generic operations.
[RFC]: https://patchwork.kernel.org/patch/4100811/
On Tuesday 13 May 2014 10:26:31 Felipe Balbi wrote:
On Thu, May 08, 2014 at 03:52:17PM +0200, Arnd Bergmann wrote:
The isp1301-omap driver cannot be built-in if the tps65010 driver
is a module, otherwise we get a link error from the reference to
the tps65010_set_vbus_draw function.
Hi,
On Tue, May 13, 2014 at 09:48:27PM +0200, Arnd Bergmann wrote:
On Tuesday 13 May 2014 10:26:31 Felipe Balbi wrote:
On Thu, May 08, 2014 at 03:52:17PM +0200, Arnd Bergmann wrote:
The isp1301-omap driver cannot be built-in if the tps65010 driver
is a module, otherwise we get a link
On 5/13/14, 10:51 AM, Javier Martinez Canillas jav...@dowhile0.org
wrote:
Hello Pantelis,
On Tue, May 13, 2014 at 7:07 PM, Pantelis Antoniou
pantelis.anton...@gmail.com wrote:
Hi Javier,
On May 13, 2014, at 7:39 AM, Javier Martinez Canillas wrote:
On Tue, May 13, 2014 at 4:22 PM, Matt
* Tony Lindgren t...@atomide.com [140509 08:31]:
* Tomi Valkeinen tomi.valkei...@ti.com [140509 01:31]:
On 09/05/14 02:33, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [140507 11:00]:
* Tomi Valkeinen tomi.valkei...@ti.com [140507 09:03]:
On 07/05/14 18:03, Tony Lindgren
* Tony Lindgren t...@atomide.com [140509 08:38]:
* Tomi Valkeinen tomi.valkei...@ti.com [140509 00:08]:
On 09/05/14 02:36, Tony Lindgren wrote:
Why always-on?
Oops, yeah that should not be there. The GPIO is board specific.
Oops, on ldp the regulator is always on tps61130rsa enabled by
Hi,
Here's an updated set of patches to enable low-power idle modes
for some omap3 boards when booted with device tree.
This series when applied on top of the patches in tread
[PATCH 00/11]
These settings are based on the Recommended Sleep Sequences for
the Zoom Platform pdf at:
http://omappedia.com/wiki/File:Recommended_Sleep_Sequences_Zoom.pdf
These settings assume most of the regulators are under control of
Linux, and twl4030 only cuts off VDD1 and VDD2 during off-idle as
Linux
The twl4030 PMIC needs to be configured properly for things like
warm reset and deeper idle states so the PMIC manages the regulators
properly based on the hardware triggers from the SoC.
For example, when rebooting an OMAP3530 at 125 MHz, it hangs.
With this patch, TWL4030 will be reset when a
We have these bits partially defined in two different
places, so let's fix them up and add defines for the
missing bits. These bits are the same for P1_SW_EVENTS,
P2_SW_EVENTS and P3_SW_EVENTS.
Cc: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off-by: Tony Lindgren t...@atomide.com
---
Looks like we can still hit the issue of wrong load order of
twl4030 configuration. If we have a sleep configuration loaded,
and do a warm reset, the device can hang while initializing the
wakeup12 sequence. We do have a warning message about wrong order
of twl4030 configuration, but in this case
N900 now seems to shut down the external oscillator when hitting
off-idle.
And Beagle XM seems to have OSC_EN pin connected to allow shutting
down the oscillator looking at the schematics. The oscillator
output is cut off in off-idle and you can monitor it from R56 on
the bottom side of the board
Some oscillators can be turned off during off-idle saving few
a little bit power at the cost of the oscillator start up
latency.
If you board can do this, you can now enable it by using the
ti,twl4030-power-idle-osc-off compatible flag.
Cc: Peter De Schrijver pdeschrij...@nvidia.com
Cc: Samuel
With the recommended twl4030 configuration added, we can now add
board specific changes as modifications to the recommended
configuration.
Note that the data is private to this driver, and the data must
always have a NULL resource in the sentinel.
Cc: Peter De Schrijver pdeschrij...@nvidia.com
Hi Javier,
On May 13, 2014, at 10:51 AM, Javier Martinez Canillas wrote:
Hello Pantelis,
On Tue, May 13, 2014 at 7:07 PM, Pantelis Antoniou
pantelis.anton...@gmail.com wrote:
Hi Javier,
On May 13, 2014, at 7:39 AM, Javier Martinez Canillas wrote:
On Tue, May 13, 2014 at 4:22 PM, Matt
Hi John,
On May 13, 2014, at 1:24 PM, John Syn wrote:
On 5/13/14, 10:51 AM, Javier Martinez Canillas jav...@dowhile0.org
wrote:
Hello Pantelis,
On Tue, May 13, 2014 at 7:07 PM, Pantelis Antoniou
pantelis.anton...@gmail.com wrote:
Hi Javier,
On May 13, 2014, at 7:39 AM, Javier
On 5/14/2014 12:07 AM, Bin Liu wrote:
Hi,
On Tue, May 13, 2014 at 8:24 AM, George Cherian george.cher...@ti.com wrote:
Hi Daniel,
On 5/13/2014 6:44 PM, Daniel Mack wrote:
Hi George,
On 05/13/2014 02:57 PM, George Cherian wrote:
I never enabled the MUSB_BABBLE_SW_SESSION_CTRL in the
On 5/13/2014 9:32 PM, Felipe Balbi wrote:
Hi,
On Thu, May 08, 2014 at 03:03:03PM +0530, George Cherian wrote:
Calculate the wrapper register offsets in a seperate function.
Improve code readability, decrease the dwc3_probe() size.
Signed-off-by: George Cherian george.cher...@ti.com
---
On 5/13/14, 8:39 PM, Pantelis Antoniou pantelis.anton...@gmail.com
wrote:
Hi John,
On May 13, 2014, at 1:24 PM, John Syn wrote:
On 5/13/14, 10:51 AM, Javier Martinez Canillas jav...@dowhile0.org
wrote:
Hello Pantelis,
On Tue, May 13, 2014 at 7:07 PM, Pantelis Antoniou
hi Arnd,
On Tuesday 13 May 2014 07:04 PM, Arnd Bergmann wrote:
On Tuesday 13 May 2014 15:27:46 Arnd Bergmann wrote:
On Tuesday 13 May 2014 18:56:23 Kishon Vijay Abraham I wrote:
If you have a case where the outbound translation is a 256MB (i.e. 28bit)
section of the CPU address space, that
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