Nishanth Menon writes:
> When viewing the /proc/interrupts, there is no information about which
> GPIO bank a specific gpio interrupt is hooked on to. This is more than a
> bit irritating as such information can esily be provided back to the
> user and at times, can be crucial for debug.
>
> So,
On Fri, Aug 22, 2014 at 05:20:24PM -0700, Tony Lindgren wrote:
> * Mark Brown [140822 17:07]:
> > > Acked-by: Tony Lindgren
> > Definitely not too late - indeed I'd have expected you to apply this.
> Sure, let me know if you prefer me to pick it up.
Yes, please.
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Description: D
* Mark Brown [140822 17:07]:
> On Fri, Aug 22, 2014 at 04:13:00PM -0700, Tony Lindgren wrote:
> > * Mark Brown [140812 10:52]:
>
> > > The kernel has never supported clk32g as a regulator since it is a clock
> > > and not a regulator. Fortunately nothing actually references this node so
> > > we
On Fri, Aug 22, 2014 at 04:13:00PM -0700, Tony Lindgren wrote:
> * Mark Brown [140812 10:52]:
> > The kernel has never supported clk32g as a regulator since it is a clock
> > and not a regulator. Fortunately nothing actually references this node so
> > we can just remove it.
> If not too late:
* Mark Brown [140812 10:52]:
> From: Mark Brown
>
> The kernel has never supported clk32g as a regulator since it is a clock
> and not a regulator. Fortunately nothing actually references this node so
> we can just remove it.
>
> Signed-off-by: Mark Brown
If not too late:
Acked-by: Tony Lind
* Grazvydas Ignotas [140806 15:57]:
> On Wed, Aug 6, 2014 at 11:02 AM, Roger Quadros wrote:
> > Hi GraÅžvydas,
> >
> > On 08/05/2014 07:15 PM, Grazvydas Ignotas wrote:
> >> On Tue, Aug 5, 2014 at 1:11 PM, Roger Quadros wrote:
> >>> For v3.12 and prior, 1-bit Hamming code ECC via software was the
* Markus Pargmann [140804 05:56]:
> When an alias for a clock already exists the warning is printed. For
> every module with a main_clk defined, a clk alias for fck is added.
> There are some components that have the same main_clk defined, so this
> is a really normal situation.
>
> For example t
* Hans Wennborg [140803 17:21]:
> Signed-off-by: Hans Wennborg
> ---
> arch/arm/mach-omap2/id.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index d42022f..53841de 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/a
* Nishanth Menon [140818 11:49]:
> On 07/30/2014 02:20 PM, Nishanth Menon wrote:
> > GPIO modules are also interrupt sources. However, they require both the
> > GPIO number and IRQ type to function properly.
> >
> > By declaring that GPIO uses interrupt-cells=<1>, we essentially do not
> > allow
* Pekon Gupta [140723 11:20]:
> Each GPMC chip-select needs to be configured for (base-address,CS-size) so
> that
> GPMC understands the address-space allocated to device connected externally.
> These chip-select configurations (base-address, CS-size) follow some basic
> mapping rules like:
> - T
* Kishon Vijay Abraham I [140821 21:52]:
> >
> > Kishon, this regression fix would be nice to get into the v3.17-rc
> > series if no objections. If you don't have other fixes, I can also
> > queue via arm-soc with proper acks.
>
> I can queue this one up once put_autosuspend() is used.
Great, t
Hi,
* Grazvydas Ignotas [140822 06:21]:
> Hi,
>
> On Thu, Aug 21, 2014 at 7:48 PM, Tony Lindgren wrote:
> > Commit 249751f22380 ("usb: phy: twl4030-usb: poll for ID disconnect")
> > added twl4030_id_workaround_work() to deal with lost interrupts
> > after ID pin goes down. However, this current
Now that ti,omap5-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark pinctrl as interrupt controller so that it can be
used with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon
---
arch/arm/boo
Add basic skeleton of OMAP pinctrl bindings. This is compatible with
pinctrl,single bindings and is meant purely as a reference point.
Signed-off-by: Nishanth Menon
---
.../bindings/pinctrl/ti,omap-pinctrl.txt |9 +
1 file changed, 9 insertions(+)
create mode 100644
Docum
We've had deeper idle states working on omaps for few years now,
but only in the legacy mode. When booted with device tree, the
wake-up events did not have a chance to work until commit
3e6cee1786a1 ("pinctrl: single: Add support for wake-up interrupts")
that recently got merged. In addition to tha
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM
And for DRA7, provide crossbar number for prm interrupt.
Signed-off-by: Nishanth Menon
---
arch/arm/boot/dts/dra7.dtsi |1 +
arch/arm/boot/dts/omap3.dtsi |1 +
arch/arm/boot/dts/omap4.dtsi |1 +
arch/arm/boot/dts/omap5.dtsi |
From: Rajendra Nayak
Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.
Signed-off-by: Rajendra Nayak
[n...@ti.com: Split and optimize]
Signed-off-by: Nishanth Menon
---
arch/arm
Now that ti,am437-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark the pinctrl as interrupt controller so that it can
be used with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon
---
arch/arm
From: Keerthy
AM437x pinctrl definitions now differ from traditional 16 bit OMAP pin
ctrl definitions, in that all 32 bits are used to describe a single pin
Also the location of wakeupenable and event bits have changed.
Signed-off-by: Keerthy
[n...@ti.com: minor updates]
Signed-off-by: Nishant
The following series are various fixes and improvements for pinctrl
for AM437x and DRA7. It also tries to add documentation for existing
pinctrl bindings for Texas Instruments' OMAP SoCs.
Functionality depends on the dts update (in series 6), PRM fixes and
the pdata quirk changes
This is part 4/6
From: Rajendra Nayak
With consolidated code, now we can add the required hooks for
DRA7 to enable power management.
Signed-off-by: Rajendra Nayak
[n...@ti.com: minor modifications]
Signed-off-by: Nishanth Menon
---
Note: Minor checkpatch warning exists for 80 char limit that was ignored.
arc
From: Santosh Shilimkar
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static
Now that ti,dra7-padconf is available, switch over to that compatible
property. Retain pinctrl-single for legacy support.
While at it, mark pinctrl as interrupt controller so that it can be used
with interrupts-extended property for wakeup events.
Signed-off-by: Nishanth Menon
---
arch/arm/boot
From: Santosh Shilimkar
In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU.
The following series add the missing dts changes needed for pinctrl to
finally work on OMAP5/DRA7.
This is part 6/6 series which eventually enables framework for
suspend-to-ram and cpuidle for OMAP5 and DRA7.
Depends on previous series for pinctrl and PRM fixes for
functionality, but is capable o
Mark rxd as wakeupcapable for 115200n8 no hardware-flow control
configuration. If h/w flow control is being used, then rts/cts
appropriately should be used.
Signed-off-by: Nishanth Menon
---
arch/arm/boot/dts/dra7-evm.dts |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts
From: Santosh Shilimkar
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.
Signed-off-by: Santosh Shilimkar
[rna...@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak
[n...@ti.com: reb
The following series are various fixes and improvements for
supporting suspend-to-ram. This depends on the following for basic
functionality:
series 1/6 where powerdomain fixes were involved.
This will at least allow wake up from an internal source such as from a wakeup
timer:
For example with
h
At 3.6Mbaud, with slightly over 2Mbit/s data coming in, we see 1600 uart
rx buffer overflows within 30 seconds. Threading the interrupt handling reduces
this to about 170 overflows in 10 minutes.
In practice this therefore reduces the need for hardware flow control,
meaning the sending side doesn'
From: Santosh Shilimkar
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.
So, isolate the function to hotplug_restart pointer i
From: Santosh Shilimkar
Add OMAP5/DRA74/72 CPUIDLE support.
This patch adds MPUSS low power states in cpuidle.
C1 - CPU0 WFI + CPU1 WFI + MPU ON
C2 - CPU0 RET + CPU1 RET + MPU CSWR
Tested on DRA74/72-EVM for C1 and C2 states.
NOTE: DRA7 does not do voltage scaling as part of r
From: Rajendra Nayak
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
Signed-off-by: Rajendra Nayak
[n...@ti.com: update to do save_state only on DRA7]
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2
From: Santosh Shilimkar
With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar
[n...@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon
---
/home/nmenon/tmp/upstream/v3.17/cpuidle-suspend-support/0009-ARM-OMAP5-
From: Santosh Shilimkar
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to
DRA7 pinctrl definitions now differ from traditional 16 bit OMAP pin
ctrl definitions, in that all 32 bits are used to describe a single pin
Also the location of wakeupenable and event bits have changed.
Signed-off-by: Nishanth Menon
---
.../bindings/pinctrl/ti,omap-pinctrl.txt |1
Provide pdata-quirks for DRA7 processor family.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/pdata-quirks.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index edacfed..827e106 100644
--- a/arch/arm/mac
Provide pdata-quirks for OMAP5 processor family.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/pdata-quirks.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index 90c88d4..edacfed 100644
--- a/arch/arm/m
The following series are various fixes and improvements for daisychain
support in OMAP5+ using pinctrl framework similar to that done for
OMAP3+
This is part 3/6 series which eventually enables framework for
suspend-to-ram and cpuidle for OMAP5 and DRA7
Each of series is based on v3.17-rc1 and th
From: Keerthy
Provide pdata-quirks for Am437x processor family.
Signed-off-by: Keerthy
---
arch/arm/mach-omap2/pdata-quirks.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index 827e106..5fea34e 100644
--- a/a
Allow the PRM interrupt information to be picked up from device tree.
OMAP3 may use legacy boot and needs to be compatible with old dtbs
(without interrupt populated), for these, we use the value which is
pre-populated.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/prm3xxx.c | 18 +
PRM device instance can vary depending on SoC. We already handle the
same during reset of the device, However, this is also needed
for other logic instances. So, first abstract this out to a generic
function.
Signed-off-by: Nishanth Menon
---
Minor note: this patch has a 'CHECK: extern prototype
OMAP5 and DRA7 can now use pinctrl based I/O daisychain wakeup
capability. So, enable the support.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/prm44xx.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
The following series are various fixes and improvements for
PRM for I/O Daisy chain support in OMAP4+ with device tree.
This is part 2/6 series which eventually enables framework for
suspend-to-ram and cpuidle for OMAP5 and DRA7
Each of series is based on v3.17-rc1 and this specific series is ava
Allow the PRM interrupt information to be picked up from device tree.
the only exception is for OMAP4 which uses values pre-populated and allows
compatibility with older dtb.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/prm44xx.c | 40
1 file c
"wkup" event at bit offset 0 exists only on OMAP3.
OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU
register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3.
The same applies to AM437x as well.
Remove the wrong definition.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap
use the generic function to pick up the prm_instance for a generic logic
which can be reused from OMAP4+
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/prm44xx.c | 47 +
1 file changed, 38 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-
powerdomain configuration in OMAP is done using PWRSTCTRL register for
each power domain. However, PRCM lets us write any value we'd like to
the logic and power domain target states, however the SoC integration
tends to actually function only at a few discrete states. These valid
states are already
Hi,
The following series are various fixes and improvements for
powerdomain support in OMAP4+.
This is part 1/6 series which eventually enables framework for
suspend-to-ram and cpuidle for OMAP5 and DRA7
Each of series is based on v3.17-rc1 and this specific series is available:
weblink:
https:
We are using power domain state as RET and logic state as OFF. This
state is OSWR. This may not always be supported on ALL power domains. In
fact, on certain power domains, this might result in a hang on certain
platforms. Instead, depend on powerdomain data to provide accurate
information about th
Not all SoCs support OFF mode - for example DRA74/72. So, use valid
power state during CPU hotplug.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/omap-mpuss-lowpower.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
b/arch/arm/mach-om
Move the logic state as different for each power domain. This allows us
to customize the deepest power state we should target over all for each
powerdomain in the follow on patches.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/pm44xx.c |5 -
1 file changed, 4 insertions(+), 1 de
Update the power domain power states for final production chip
capability. OFF mode, OSWR etc have been descoped for various domains.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/powerdomains54xx_data.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/a
DRA7 supports only CSWR for CPU, MPU power domains. Core power domain
supports upto INA.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/powerdomain.h |1 +
arch/arm/mach-omap2/powerdomains7xx_data.c | 14 +++---
2 files changed, 8 insertions(+), 7 deletions(-)
diff
No need to invoke callback when the clkdm pointer is NULL.
Signed-off-by: Nishanth Menon
---
arch/arm/mach-omap2/powerdomain.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach-omap2/powerdomain.c
index faebd5f..f391948 10
Hi,
On Thu, Aug 21, 2014 at 7:48 PM, Tony Lindgren wrote:
> Commit 249751f22380 ("usb: phy: twl4030-usb: poll for ID disconnect")
> added twl4030_id_workaround_work() to deal with lost interrupts
> after ID pin goes down. However, this currently only works for the
> insertion. The PHY interrupts
From: Daniel Mack
This patch makes the edma driver resume correctly after suspend. Tested
on an AM33xx platform with cyclic audio streams and omap_hsmmc.
All information can be reconstructed by already known runtime
information.
As we now use some functions that were previously only used from _
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