On Mon, 01 Sep 2014, Nishanth Menon wrote:
On 09/01/2014 04:32 AM, Lee Jones wrote:
On Fri, 29 Aug 2014, Nishanth Menon wrote:
On 08/29/2014 05:56 AM, Lee Jones wrote:
On Tue, 19 Aug 2014, Nishanth Menon wrote:
With the recent pinctrl-single changes, omaps can treat wake-up events
from
The quite-recently-added analog-tv-connector bindings say that the
compatible string for composite video connector is
composite-connector. That string is also used in the omap3-n900.dts
file. However, the connector driver uses composite-video-connector, so
this has never worked.
While changing
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual AHB clock. So add support for the same.
Signed-off-by: Vivek
On Tue, Sep 02, 2014 at 11:39:08AM +0100, Vivek Gautam wrote:
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual
NAND uses wait pin only to indicate device readiness after
a block/page operation. It is not use to extend individual
read/write cycle and so read/write wait pin monitoring must
be disabled for NAND.
This patch also gets rid of the below warning when NAND is
accessed for the first time.
Both QSPI and GPMC-NAND share the same Pin (A8) from the SoC for Chip Select
functionality. So both can't be enabled simultaneously.
Disable QSPI node to prevent the pin conflict as well as
be similar to 3.12 release.
CC: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Roger Quadros
For NAND read write wait pin monitoring must be kept disabled as the
wait pin is only used to indicate NAND device ready status and not to
extend each read/write cycle.
So don't print a warning if wait pin is specified while read/write
monitoring is not in the device tree.
Sanity check wait pin
Hi Tony,
These are some of the issues I found while testing v3.17-rc3.
- Wrong ECC scheme used for am43x GP and EPOS evm. We need to use
BCH16 instead of BCH8.
- Wrong read/write wait pin monitoring setting used for NAND
resulting in L3 application error debug message on console.
- Pin
am43x-epos-evm uses a NAND chip with page size 4096 bytes
and spare area of 225 bytes per page.
For such a setup it is preferrable to use BCH16 ECC scheme over
BCH8. This also makes it compatible with ROM code ECC scheme so
we can boot with NAND after flashing from kernel.
Signed-off-by: Roger
am437x-gp-evm uses a NAND chip with page size 4096 bytes
and spare area of 225 bytes per page.
For such a setup it is preferrable to use BCH16 ECC scheme over
BCH8. This also makes it compatible with ROM code ECC scheme so
we can boot with NAND after flashing from kernel.
Signed-off-by: Roger
NAND uses wait pin only to indicate device readiness after
a block/page operation. It is not use to extend individual
read/write cycle and so read/write wait pin monitoring must
be disabled for NAND.
Add gpmc wait pin information as the NAND uses wait pin 0
for device ready indication.
On Tue, Sep 02, 2014 at 04:09:08PM +0530, Vivek Gautam wrote:
Hi,
On Fri, Aug 29, 2014 at 12:18 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Thu, Aug 28, 2014 at 09:01:56AM +0100, Vivek Gautam wrote:
Exynos7 also has a separate special gate clock going to the IP
apart from the usual
On Mon, Sep 01, 2014 at 01:30:21PM +0530, Vivek Gautam wrote:
On Thu, Aug 28, 2014 at 8:36 PM, Daniele Forsi dfo...@gmail.com wrote:
2014-08-28 10:02 GMT+02:00 Vivek Gautam:
This USB 3.0 PHY controller is also present on Exynos7
platform, so adding the dependency on ARCH_EXYNOS7 for this
Hi,
On Tue, Sep 02, 2014 at 12:18:12PM +0100, Peter Griffin wrote:
Hi Felipe,
Sorry for the delay in replying to this mail, I've been trying to get
answers to the suspend/resume questions you had.
np
+config USB_DWC3_ST
+ tristate STMicroelectronics Platforms
+ depends on ARCH_STI
* kpark3...@gmail.com kpark3...@gmail.com [140826 01:29]:
From: Sahara keun-o.p...@windriver.com
Since OMAP low-level debug code places data in the .data section,
The symbol DEBUG_UNCOMPRESS was defined with !DEBUG_OMAP2PLUS_UART.
This patch removes the part using data section in
* Sebastian Reichel s...@kernel.org [140901 20:06]:
Hi,
On Mon, Sep 01, 2014 at 07:47:53PM +0200, Sebastian Andrzej Siewior wrote:
On 08/29/2014 06:12 PM, Tony Lindgren wrote:
Looks like the paste bug is there for sure, doing off idle and pasting
240 characters to the console can hang
This patch adds the new dwc3-st.c glue driver found on
STMicroelectronics stih407 consumer electronics SoC's into the STI
arch section of the maintainers file.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
MAINTAINERS | 1 +
1 file changed, 1
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It manages the powerdown signal,
and configures the internal glue logic and syscfg registers.
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
Signed-off-by: Peter Griffin peter.grif...@linaro.org
Acked-by: Lee
This patch documents the device tree documentation required for
the ST usb3 controller glue layer found in STiH407 devices.
Signed-off-by: Giuseppe Cavallaro peppe.cavall...@st.com
Signed-off-by: Peter Griffin peter.grif...@linaro.org
Acked-by: Lee Jones lee.jo...@linaro.org
---
This series adds support for the ST glue logic which wraps the DWC3 controller
on STiH407 SoC family chipsets.
Changes since v4
- Fix bug with setting bits in usb control register
- Remove superflous '\n'
- Change default Kconfig to make default same as other platforms
- Update dt doc example
Hi Roger,
On Tuesday 02 September 2014 07:27 PM, Roger Quadros wrote:
Hi Tony,
These are some of the issues I found while testing v3.17-rc3.
- Wrong ECC scheme used for am43x GP and EPOS evm. We need to use
BCH16 instead of BCH8.
Thanks for updating ECC scheme for AM43x EVM boards.
Just for
On Tuesday 02 September 2014 07:27 PM, Roger Quadros wrote:
am43x-epos-evm uses a NAND chip with page size 4096 bytes
and spare area of 225 bytes per page.
For such a setup it is preferrable to use BCH16 ECC scheme over
BCH8. This also makes it compatible with ROM code ECC scheme so
we can boot
On Tuesday 02 September 2014 07:27 PM, Roger Quadros wrote:
am437x-gp-evm uses a NAND chip with page size 4096 bytes
and spare area of 225 bytes per page.
For such a setup it is preferrable to use BCH16 ECC scheme over
BCH8. This also makes it compatible with ROM code ECC scheme so
we can boot
On 09/01/2014 07:47 PM, Sebastian Andrzej Siewior wrote:
Comparing it with serial-omap I see the same thing: I takes approx the
same amount of data until the first one is displayed. After a lot of
long writes which wake the chip up from idle I manage to freeze both,
the serial-omap driver and
Hi Roger,
On Tuesday 02 September 2014 07:27 PM, Roger Quadros wrote:
NAND uses wait pin only to indicate device readiness after
a block/page operation. It is not use to extend individual
read/write cycle and so read/write wait pin monitoring must
be disabled for NAND.
I think this is
On Tuesday 02 September 2014 07:27 PM, Roger Quadros wrote:
For NAND read write wait pin monitoring must be kept disabled as the
wait pin is only used to indicate NAND device ready status and not to
extend each read/write cycle.
I think this description, does not fit in this patch.
And is
* Sebastian Andrzej Siewior bige...@linutronix.de [140902 11:40]:
On 09/01/2014 07:47 PM, Sebastian Andrzej Siewior wrote:
Comparing it with serial-omap I see the same thing: I takes approx the
same amount of data until the first one is displayed. After a lot of
long writes which wake the
On Tue, Sep 02, 2014 at 01:15:37PM -0700, Tony Lindgren wrote:
* Sebastian Andrzej Siewior bige...@linutronix.de [140902 11:40]:
On 09/01/2014 07:47 PM, Sebastian Andrzej Siewior wrote:
Comparing it with serial-omap I see the same thing: I takes approx the
same amount of data until the
Hi Tomi,
Thank you for the patch.
On Tuesday 02 September 2014 10:35:46 Tomi Valkeinen wrote:
The quite-recently-added analog-tv-connector bindings say that the
compatible string for composite video connector is
composite-connector. That string is also used in the omap3-n900.dts
file.
Here are some basic OMAP test results for Linux v3.17-rc3.
Logs and other details at:
http://www.pwsan.com/omap/testlogs/test_v3.17-rc3/20140902165525/
Test summary
Build: zImage:
Pass (16/16): multi_v7_defconfig, omap2plus_defconfig,
* Sebastian Andrzej Siewior sebast...@breakpoint.cc [140902 01:29]:
On 2014-08-19 08:24:05 [-0700], Tony Lindgren wrote:
This allows us to enable the PMIC configuration for n900.
Fixes: 43fef47f94a1 (mfd: twl4030-power: Add a configuration to turn off
oscillator during off-idle)
On Fri, Aug 29, 2014 at 12:58 AM, Felipe Balbi ba...@ti.com wrote:
On Thu, Aug 28, 2014 at 01:31:59PM +0530, Vivek Gautam wrote:
The Exynos-DWC3 USB 3.0 DRD controller is also present on
Exynos7 platform, so adding the dependency on ARCH_EXYNOS7
for this driver.
Signed-off-by: Vivek Gautam
On Tue, Sep 2, 2014 at 8:07 PM, Felipe Balbi ba...@ti.com wrote:
On Mon, Sep 01, 2014 at 01:30:21PM +0530, Vivek Gautam wrote:
On Thu, Aug 28, 2014 at 8:36 PM, Daniele Forsi dfo...@gmail.com wrote:
2014-08-28 10:02 GMT+02:00 Vivek Gautam:
This USB 3.0 PHY controller is also present on
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