Hi Mark,
On 13/11/14 00:23, Mark Brown wrote:
On Wed, Nov 12, 2014 at 04:40:51PM +0200, Jyri Sarha wrote:
It would make the most sense to get these in trough fbdev tree. So it
would be nice to get acked-bys (if the patches are Ok) for ASoC side
changes from appropriate maintainers.
So,
Hi Suman,
On Wed, Nov 12, 2014 at 9:50 PM, Suman Anna s-a...@ti.com wrote:
None of the OMAPs have multiple IP instances, and as such the base-id is
an optional property. I have made this change to make sure we atleast
attempt to use the value if mentioned in DT and not hard-coding the
value
On Thu, 13 Nov 2014 10:05:28 +0200
Tomi Valkeinen tomi.valkei...@ti.com wrote:
[snip]
I don't have much knowledge of the asoc architecture, so I probably
can't comment much on the sound/ side design. For me the most important
things are that 1) it works 2) I can easily unload/load the
Hi,
On 13/11/14 11:17, Jean-Francois Moine wrote:
On Thu, 13 Nov 2014 10:05:28 +0200
Tomi Valkeinen tomi.valkei...@ti.com wrote:
[snip]
I don't have much knowledge of the asoc architecture, so I probably
can't comment much on the sound/ side design. For me the most important
things
Tony,
On Thu, 6 Nov 2014, Tony Lindgren wrote:
Any comments on the patch below? Let me know if you want to keep the
devm stuff out of kernel/irq/manage.c.
Sorry, this slipped through the cracks.
+static int setup_wakeirq(struct device *dev, unsigned int wakeirq,
+
Hi Suman,
On Wed, Nov 12, 2014 at 9:32 PM, Suman Anna s-a...@ti.com wrote:
Is this the validation you mentioned which requires the existence of
hwspinlock/core: maintain a list of registered hwspinlock banks ?
Well, not exactly. The validation is on the following segment,
+ id =
On Tue, 11 Nov 2014, R, Vignesh wrote:
On Tue, 11 Nov 2014, Vignesh R wrote:
In one shot mode, sequencer automatically disables all enabled steps
at the end of each cycle. (both ADC steps and TSC steps) Hence these
steps need not be saved in reg_se_cache for clearing these steps at a
On 11/07/2014 03:49 PM, Roger Quadros wrote:
We want to have more data than just can_dev_id to be present
in the driver data e.g. TI platforms need RAMINIT register
description. Introduce the c_can_driver_data structure and move
the can_dev_id into it.
Tidy up the way it is used on probe().
On 11/07/2014 03:49 PM, Roger Quadros wrote:
Some platforms (e.g. TI) need special RAMINIT register handling.
Provide a way to store RAMINIT register description in driver data.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/net/can/c_can/c_can.h | 6 ++
On 11/07/2014 03:49 PM, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more insanity, this register is shared with other
IPs like DSS, PCIe and PWM.
Provides a more
On 11/12/2014 08:02 PM, Tony Lindgren wrote:
* pekon pe...@pek-sem.com [141109 11:31]:
On Saturday 08 November 2014 04:18 AM, Tony Lindgren wrote:
Right. I doubt anybody has bch8 rootfs on LDP.. And considering u-boot
must be ham1 to boot at all, that's what we should change for the
devices
On 12/11/14 17:02, Tony Lindgren wrote:
And, with a quick grep, I see CONTROL_DEVCONF1 touched in multiple
places in the kernel. I wonder if adding a pinmux entry for it could
cause some rather odd problems.
They can all use pinctrl-single no problem.
Can, but don't. That's my worry. If we
On 13/11/14 00:10, Marek Belisko wrote:
opa362 is amplifier for video and can be connected to the tvout pads
of the OMAP3. It has one gpio control for enable/disable of the output
(high impedance).
Signed-off-by: H. Nikolaus Schaller h...@goldelico.com
---
On 11/09/2014 09:29 PM, pekon wrote:
On Saturday 08 November 2014 04:18 AM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [141107 01:59]:
On 11/07/2014 11:35 AM, Roger Quadros wrote:
On 11/06/2014 08:03 PM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [141105 03:02]:
In commit
On 11/13/2014 01:09 PM, Marc Kleine-Budde wrote:
On 11/07/2014 03:49 PM, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more insanity, this register is shared with other
IPs
The SoC supports 2 DCAN nodes. Add them.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5fd52cd..631b5fb 100644
---
Hi Tony,
These patches add CAN support for am33xx, am43xx and dra7 platforms.
They can go in independent of [1] but depend on [1] for functionality.
Tested on am335x-evm, am437x-gp-evm and dra7-evm.
NOTE:
- for DCAN to work on DRA7 we need this patch to keep the CAN PHY powered.
The board has 2 CAN ports but only the first one can be used.
Enable the first CAN port.
WAKEUP0 pin doesn't have INPUT enable bit so we just disable
weak PULLs.
The second CAN port cannot be used without hardware modification
so we don't enable the second port.
Signed-off-by: Roger Quadros
Use syscon regmap to expose the Control module register space.
This register space is shared between many users e.g. DCAN, USB, display, etc.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git
From: Mugunthan V N mugunthan...@ti.com
Add DCAN support for AM437x GP EVM with both DCAN instances.
[Roger Q] Updated output pin to not use pull up.
Signed-off-by: Mugunthan V N mugunthan...@ti.com
Signed-off-by: George Cherian george.cher...@ti.com
Signed-off-by: Sekhar Nori nsek...@ti.com
Use syscon regmap to expose the Control module register space.
This register space is shared between many users e.g. DCAN, USB, display, etc.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git
Display and DCAN drivers use syscon regmap to access some registers
in the CORE control area. Add the syscon regmap node for this
area.
Cc: Tomi Valkeinen tomi.valkei...@ti.com
Cc: Nishanth Menon n...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 5 +
1
The board has 2 CAN ports but only the first one can be used.
Enable the first CAN port.
WAKEUP0 pin doesn't have INPUT enable bit so we just disable
weak PULLs.
The second CAN port cannot be used without hardware modification
so we don't enable the second port.
Signed-off-by: Roger Quadros
DCAN1 is routed to CAN port (J11) when Profile 1 is selected on the
profile selection switch.
Provide information for DCAN1 pins and node but keep it disabled
by default. User has to manually enable it if Profile 1 is chosen.
Signed-off-by: Roger Quadros rog...@ti.com
---
The SoC contains 2 DCAN modules. Add them.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 899c57c..12fb1db 100644
---
Add raminit-syscon property to specify the RAMINIT register.
Add clock information.
Rename can nodes from d_can to can to be compliant
with the ePAPR specs.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/am33xx.dtsi | 20
1 file changed, 12 insertions(+), 8
Hi,
On Wednesday 12 November 2014 06:30 PM, Johannes Pointner wrote:
Hello Vignesh,
I tried your patch version 3 on a customized board and had some
behavior I couldn't explain.
If I only use the touchscreen it works fine but if I also read values
from the ADCs then I get a lot of pen_up
On 11/07/2014 03:49 PM, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more insanity, this register is shared with other
IPs like DSS, PCIe and PWM.
Provides a more
On 11/12/2014 03:16 PM, Roger Quadros wrote:
DRA7 CAN IP suffers from a problem which causes it to be prevented
from fully turning OFF (i.e. stuck in transition) if the module was
disabled while there was traffic on the CAN_RX line.
To work around this issue we select the SLEEP pin state by
Added HS200 to improve EMMC throughput for dra72.
With HS200
==
Read throughput
./dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100 oflag=sync
100+0 records in
100+0 records out
104857600 bytes (105 MB) copied, 1.46028 s, 71.8 MB/s
Write throughput
root@dra7xx-evm:/# ./dd if=/dev/zero
Added HS200 to improve EMMC throughput for dra72.
With HS200
==
Read throughput
./dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100 oflag=sync
100+0 records in
100+0 records out
104857600 bytes (105 MB) copied, 1.46028 s, 71.8 MB/s
Write throughput
root@dra7xx-evm:/# ./dd if=/dev/zero
From: Balaji T K balaj...@ti.com
MMC tuning procedure is required to support SD card
UHS1-SDR104 mode and EMMC HS200 mode.
The tuning function omap_execute_tuning() will only
be called by the MMC/SD core if the corresponding
speed modes are supported by the OMAP silicon which
is set in the mmc
On 11/13/2014 01:09 PM, Roger Quadros wrote:
What about the existing device trees that don't have the syscon-raminit
phandle? We can either keep the existing init routines or create regmap
in the platform driver an use the new ones.
There is only one user
arch/arm/boot/dts/am33xx.dtsi
Set the maximum operating frequency of MMC2 to 192MHz.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index abbaaa7..5cc1110 100644
From: Viswanath Puttagunta vi...@ti.com
set SDR104, SDR50, DDR50 and HS200 capability flags to caps/caps2 by reading
MMCHS_CAPA2 register.
Signed-off-by: Viswanath Puttagunta vi...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
On 11/13/2014 02:56 PM, Marc Kleine-Budde wrote:
On 11/12/2014 03:16 PM, Roger Quadros wrote:
DRA7 CAN IP suffers from a problem which causes it to be prevented
from fully turning OFF (i.e. stuck in transition) if the module was
disabled while there was traffic on the CAN_RX line.
To work
On 11/13/2014 02:44 PM, Marc Kleine-Budde wrote:
On 11/07/2014 03:49 PM, Roger Quadros wrote:
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more insanity, this register is shared with other
IPs
From: Tomasz Figa t.f...@samsung.com
On Exynos SoCs it is necessary to resume operation of L2C early in
assembly code, because otherwise certain systems will crash. This patch
adds necessary code to non-secure resume handler.
Signed-off-by: Tomasz Figa t.f...@samsung.com
[rewrote the code
From: Tomasz Figa t.f...@samsung.com
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step
From: Tomasz Figa t.f...@samsung.com
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +
From: Tomasz Figa t.f...@samsung.com
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine
From: Tomasz Figa t.f...@samsung.com
Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure
From: Tomasz Figa t.f...@samsung.com
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an
From: Tomasz Figa t.f...@samsung.com
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only from secure mode.
First four patches extend
On 11/13/2014 01:22 PM, Roger Quadros wrote:
The SoC contains 2 DCAN modules. Add them.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi
On 11/13/2014 04:07 PM, Marc Kleine-Budde wrote:
On 11/13/2014 01:22 PM, Roger Quadros wrote:
The SoC contains 2 DCAN modules. Add them.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git
On 11/13/2014 03:40 PM, Roger Quadros wrote:
On 11/13/2014 04:07 PM, Marc Kleine-Budde wrote:
On 11/13/2014 01:22 PM, Roger Quadros wrote:
The SoC contains 2 DCAN modules. Add them.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/am4372.dtsi | 22 ++
1
On 11/13/2014 04:44 PM, Marc Kleine-Budde wrote:
On 11/13/2014 03:40 PM, Roger Quadros wrote:
On 11/13/2014 04:07 PM, Marc Kleine-Budde wrote:
On 11/13/2014 01:22 PM, Roger Quadros wrote:
The SoC contains 2 DCAN modules. Add them.
Signed-off-by: Roger Quadros rog...@ti.com
---
On 11/13/2014 03:49 PM, Roger Quadros wrote:
On 11/13/2014 04:44 PM, Marc Kleine-Budde wrote:
On 11/13/2014 03:40 PM, Roger Quadros wrote:
On 11/13/2014 04:07 PM, Marc Kleine-Budde wrote:
On 11/13/2014 01:22 PM, Roger Quadros wrote:
The SoC contains 2 DCAN modules. Add them.
Signed-off-by:
From: Viswanath Puttagunta vi...@ti.com
set SDR104, SDR50, DDR50 and HS200 capability flags to caps/caps2 by reading
MMCHS_CAPA2 register.
Signed-off-by: Viswanath Puttagunta vi...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Set the maximum operating frequency of MMC2 to 192MHz.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra72-evm.dts |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index abbaaa7..5cc1110 100644
On 11/13/2014 12:00 PM, Tomi Valkeinen wrote:
Hi,
On 13/11/14 11:17, Jean-Francois Moine wrote:
On Thu, 13 Nov 2014 10:05:28 +0200
Tomi Valkeinen tomi.valkei...@ti.com wrote:
...
and I saw only a few dependencies between the 2 subsystems:
- the CODEC must know the transmitter parameters
From: Balaji T K balaj...@ti.com
MMC tuning procedure is required to support SD card
UHS1-SDR104 mode and EMMC HS200 mode.
The tuning function omap_execute_tuning() will only
be called by the MMC/SD core if the corresponding
speed modes are supported by the OMAP silicon which
is set in the mmc
Hi,
Sorry for sending this multiple times. There was some problem with my mail
configuration which I have fixed now.
Thanks
Kishon
On Thursday 13 November 2014 08:24 PM, Kishon Vijay Abraham I wrote:
Added HS200 to improve EMMC throughput for dra72.
With HS200
==
Read
Added HS200 to improve EMMC throughput for dra72.
With HS200
==
Read throughput
./dd if=/dev/mmcblk0 of=/dev/null bs=1M count=100 oflag=sync
100+0 records in
100+0 records out
104857600 bytes (105 MB) copied, 1.46028 s, 71.8 MB/s
Write throughput
root@dra7xx-evm:/# ./dd if=/dev/zero
On Thu, 13 Nov 2014 12:00:41 +0200
Tomi Valkeinen tomi.valkei...@ti.com wrote:
[snip]
Jyri or Peter knows this better, but I think one difference with OMAP
HDMI case and tda998x is that tda998x is an external encoder, and you
transfer audio data to it via i2s or spdif, whereas OMAP
DRA7 CAN IP suffers from a problem which causes it to be prevented
from fully turning OFF (i.e. stuck in transition) if the module was
disabled while there was traffic on the CAN_RX line.
To work around this issue we select the SLEEP pin state by default
on probe and use the DEFAULT pin state on
On 13/11/14 17:00, Jean-Francois Moine wrote:
When the tda998x is not operational, the CODEC knows it and reports an
error to the audio subsystem on device open. But, once the tda998x has
been started, it always stays operational, even without HDMI connection.
What does started mean here?
On 11/13/2014 06:29 AM, Roger Quadros wrote:
On 11/12/2014 08:02 PM, Tony Lindgren wrote:
* pekon pe...@pek-sem.com [141109 11:31]:
On Saturday 08 November 2014 04:18 AM, Tony Lindgren wrote:
Right. I doubt anybody has bch8 rootfs on LDP.. And considering u-boot
must be ham1 to boot at all,
On Thu, Nov 13, 2014 at 02:22:50PM +0200, Roger Quadros wrote:
Add raminit-syscon property to specify the RAMINIT register.
Add clock information.
Rename can nodes from d_can to can to be compliant
with the ePAPR specs.
Signed-off-by: Roger Quadros rog...@ti.com
---
On 11/13/2014 04:23 PM, Roger Quadros wrote:
DRA7 CAN IP suffers from a problem which causes it to be prevented
from fully turning OFF (i.e. stuck in transition) if the module was
disabled while there was traffic on the CAN_RX line.
To work around this issue we select the SLEEP pin state by
On Fri, Nov 07, 2014 at 04:49:22PM +0200, Roger Quadros wrote:
AM3352 SoC has 2 DCAN modules. Add compatible id and
raminit driver data for am3352 DCAN.
Signed-off-by: Roger Quadros rog...@ti.com
Acked-by: Wolfram Sang w...@the-dreams.de
signature.asc
Description: Digital signature
Hi!
I actually had pm=0 on the command line, but I removed it now, and no
change: [...]
Let me try with explicit =1. .. aha, that helps. Thanks!
mh seems I actually missed to make 1 the default value. I will
prepare a patch for that.
I assume, that the example ofono commands work
On Fri 2014-11-07 09:04:52, Ivaylo Dimitrov wrote:
On 7.11.2014 01:01, Pali Rohár wrote:
For voice calls you need:
* kernel driver cmt-speech (or it has some new name)
* cmt-speech userspace library (communication with kernel)
* pulseaudio modules which are using that library
Hi,
Am 13.11.2014 um 12:51 schrieb Tomi Valkeinen tomi.valkei...@ti.com:
On 13/11/14 00:10, Marek Belisko wrote:
opa362 is amplifier for video and can be connected to the tvout pads
of the OMAP3. It has one gpio control for enable/disable of the output
(high impedance).
Signed-off-by: H.
On 13/11/14 18:25, Dr. H. Nikolaus Schaller wrote:
Hi,
Am 13.11.2014 um 12:51 schrieb Tomi Valkeinen tomi.valkei...@ti.com:
On 13/11/14 00:10, Marek Belisko wrote:
opa362 is amplifier for video and can be connected to the tvout pads
of the OMAP3. It has one gpio control for enable/disable
On Fri, 3 Oct 2014, Tero Kristo wrote:
OMAP3+ DPLL code is currently using set_rate op to change DPLL rates.
This is kind of wrong, as it also involves changing DPLL parent in certain
cases (switch between locked mode - bypass mode.) This set fixes these
issues by introducing the support of
Hi Ohad,
On 11/13/2014 04:03 AM, Ohad Ben-Cohen wrote:
Hi Suman,
On Wed, Nov 12, 2014 at 9:32 PM, Suman Anna s-a...@ti.com wrote:
Is this the validation you mentioned which requires the existence of
hwspinlock/core: maintain a list of registered hwspinlock banks ?
Well, not exactly. The
* Thomas Gleixner t...@linutronix.de [141113 02:04]:
Tony,
On Thu, 6 Nov 2014, Tony Lindgren wrote:
Any comments on the patch below? Let me know if you want to keep the
devm stuff out of kernel/irq/manage.c.
Sorry, this slipped through the cracks.
No problem I should have posted it
Hi Ohad,
On 09/16/2014 01:33 PM, Suman Anna wrote:
The buffers to be used for communication are allocated during the
rpmsg virtio driver's probe, and the total number of buffers is
currently hard-coded to 512. The vring configuration can vary from
one platform to another or between different
* Pavel Machek pa...@ucw.cz [141113 08:23]:
Hi!
I actually had pm=0 on the command line, but I removed it now, and no
change: [...]
Let me try with explicit =1. .. aha, that helps. Thanks!
mh seems I actually missed to make 1 the default value. I will
prepare a patch for
* Marc Kleine-Budde m...@pengutronix.de [141113 06:55]:
On 11/13/2014 03:49 PM, Roger Quadros wrote:
On 11/13/2014 04:44 PM, Marc Kleine-Budde wrote:
On 11/13/2014 03:40 PM, Roger Quadros wrote:
On 11/13/2014 04:07 PM, Marc Kleine-Budde wrote:
On 11/13/2014 01:22 PM, Roger Quadros wrote:
* Tom Rini tr...@ti.com [141113 08:02]:
On 11/13/2014 06:29 AM, Roger Quadros wrote:
On 11/12/2014 08:02 PM, Tony Lindgren wrote:
Right no objections to using BCH8 for rootfs, except it stopped working
over past year or so.
This would be BCH8-sw on OMAP3 right? AM3xx uses BCH8-hw and
The HDMI node does not have a power supply attached. As a result its
power regulator, VDAC, shuts off on boot and screen loses signal.
This attaches VDAC (vdda_hdmi_dac) to HDMI's vdda-supply.
Signed-off-by: Adam YH Lee adam.yh@gmail.com
---
arch/arm/boot/dts/omap4-duovero-parlor.dts | 1 +
Hi,
On Thu, Nov 13, 2014 at 09:45:36AM -0800, Tony Lindgren wrote:
* Pavel Machek pa...@ucw.cz [141113 08:23]:
OTOH ofono seems pretty reasonable. So I played a bit, and result
is python/pygtk gui which can receive an sms, initiate a call, and
report missed call. If someone wants to play,
* Tomi Valkeinen tomi.valkei...@ti.com [141113 03:33]:
On 12/11/14 17:02, Tony Lindgren wrote:
And, with a quick grep, I see CONTROL_DEVCONF1 touched in multiple
places in the kernel. I wonder if adding a pinmux entry for it could
cause some rather odd problems.
They can all use
On 11/05/2014 08:43 PM, Lennart Sorensen wrote:
I managed to get something dma related on uart3. But it isn't happy:
[ 95.577401] DMA misaligned error with device 53
repeated many times.
I wonder if the dma support isn't quite working for the omap572x yet in
this tree (ti's 3.12.y
Hi Suman,
On Thu, Nov 13, 2014 at 7:38 PM, Suman Anna s-a...@ti.com wrote:
No, not always, because, either of them can be optional between
different platform implementations. For example, on OMAP, the number of
locks is read from an IP register, and not coded in DT. Similarly,
base_id can be
Hi Ohad,
On 11/13/2014 01:45 PM, Ohad Ben-Cohen wrote:
Hi Suman,
On Thu, Nov 13, 2014 at 7:38 PM, Suman Anna s-a...@ti.com wrote:
No, not always, because, either of them can be optional between
different platform implementations. For example, on OMAP, the number of
locks is read from an IP
On Thu, Nov 13, 2014 at 07:34:09PM +0100, Sebastian Andrzej Siewior wrote:
misaligned dma? I haven't seen any alignment requirement for SDMA/EDMA
and I haven't seen this error on beagle board, am335x-evm or dra7-evm.
Well I am using the am5728, so it should be the same as the dra7-evm.
So
On Thu, 13 Nov 2014, Tony Lindgren wrote:
Oops thanks for catching that. As the devres stuff is separate, I've
updated the patch to keep it that way by adding a minimal manage.h.
This avoids including internals.h in devres.c. Does that seem usable
for you?
What's wrong with internals.h?
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1:
Linux 3.18-rc1 (2014-10-19 18:08:38 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending.git
Hi
On Thu, 13 Nov 2014, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [141113 03:33]:
On 12/11/14 17:02, Tony Lindgren wrote:
And, with a quick grep, I see CONTROL_DEVCONF1 touched in multiple
places in the kernel. I wonder if adding a pinmux entry for it could
cause
* Thomas Gleixner t...@linutronix.de [141113 14:27]:
On Thu, 13 Nov 2014, Tony Lindgren wrote:
Oops thanks for catching that. As the devres stuff is separate, I've
updated the patch to keep it that way by adding a minimal manage.h.
This avoids including internals.h in devres.c. Does that
* Paul Walmsley p...@pwsan.com [141113 15:01]:
Hi
On Thu, 13 Nov 2014, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [141113 03:33]:
On 12/11/14 17:02, Tony Lindgren wrote:
And, with a quick grep, I see CONTROL_DEVCONF1 touched in multiple
places in the kernel.
On Tuesday 04 November 2014 04:45 PM, Vignesh R wrote:
This series of patches enable ADC on am437x-gp-evm and am43x-epos-evm.
The ADC clock hwmod data of am33xx has been moved to commom place so that
both am43xx and am33xx can reuse them.
tscadc DT node has been adided to am437x-gp and
From: Brad Griffis bgrif...@ti.com
This patch makes the initial changes required to workaround TSC-false
pen-up interrupts. It is required to implement these changes in order to
remove udelay in the TSC interrupt handler and false pen-up events.
The charge step is to be executed immediately after
The charge delay value is by default 0x400. But it can be set to lower
values on some boards, as long as false pen-ups are avoided. Lowering the
value increases the sampling rate (though current sampling rate is
sufficient for TSC operation). In some boards, the value has to be
increased to avoid
This patch reads charge delay from tsc DT node and writes to
REG_CHARGEDELAY register. If the charge delay is not specified in DT
then default value of 0x400(CHARGEDLY_OPENDLY) is used.
Signed-off-by: Vignesh R vigne...@ti.com
---
drivers/input/touchscreen/ti_am335x_tsc.c | 8 +++-
1 file
In one shot mode, sequencer automatically disables all enabled steps at
the end of each cycle. (both ADC steps and TSC steps) Hence these steps
need not be saved in reg_se_cache for clearing these steps at a later
stage.
Also, when ADC wakes up Sequencer should not be busy executing any of the
From: Brad Griffis bgrif...@ti.com
TSC interrupt handler had udelay to avoid reporting of false pen-up
interrupt to user space. This patch implements workaround suggesting in
Advisory 1.0.31 of silicon errata for am335x, thus eliminating udelay
and touchscreen lag. This also improves performance
This series of patches fix TSC defects related to lag in touchscreen
performance and cursor jump at touch release. The lag was result of
udelay in TSC interrupt handler. Cursor jump due to false pen-up event.
The patches implement Advisory 1.0.31 in silicon errata of am335x-evm
to avoid false
Previously, delta filtering was applied TSC co-ordinate readouts before
reporting a single value to user space. This patch replaces delta filtering
with median filtering. Median filtering sorts co-ordinate readouts, drops min
and max values, and reports the average of remaining values. This method
On 31 October 2014 12:33, Peter De Schrijver pdeschrij...@nvidia.com wrote:
On Thu, Oct 30, 2014 at 11:48:26AM +0100, Tomeu Vizoso wrote:
Hello,
this fifth version of the series has just one change, suggested by Stephen:
Hi Mike, how is this looking for 3.19?
Regards,
Tomeu
* Initialize
On 13.11.2014 18:24, Pavel Machek wrote:
On Fri 2014-11-07 09:04:52, Ivaylo Dimitrov wrote:
Sebastian is quiet, can we have the patch? :-).
Sure, why not :)
https://gitorious.org/linux-n900/freemangordons-linux-n900/commits/30e9a5c498a89cea4c29523f69e436bf0af3c631
commits 89ce13b,
On 10/30, Tomeu Vizoso wrote:
Moves clock state to struct clk_core, but takes care to change as little API
as
possible.
struct clk_hw still has a pointer to a struct clk, which is the
implementation's per-user clk instance, for backwards compatibility.
The struct clk that
Hi Suman,
On Thu, Nov 13, 2014 at 11:02 PM, Suman Anna s-a...@ti.com wrote:
OK, lets take an example. I have say 2 device instances, say
hwlock1: hwlock@0 {
hwlock-num-locks = 32
hwlock-base-id = 0;
#hwlock-cells = 1;
};
On 11/14/2014 01:58 AM, Tony Lindgren wrote:
* Paul Walmsley p...@pwsan.com [141113 15:01]:
Hi
On Thu, 13 Nov 2014, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [141113 03:33]:
On 12/11/14 17:02, Tony Lindgren wrote:
And, with a quick grep, I see CONTROL_DEVCONF1 touched in
Hi!
Do you have an example client that can talk to ofonod?
I have not yet played with userland stuff. You could try
telepathy-ring, which integrates the ofono into the telepathy
framework.
Ok, I took a look, and telepathy-ring is not in debian, and has
a lot of
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