DESCRIPTION
Spurious Thermal Alert: Talert can happen randomly while the device remains
under the temperature limit
defined for this event to trig. This spurious event is caused by a incorrect
re-synchronization between
clock domains. The comparison between configured threshold and current
Bandgap Temperature read Dtemp can be corrupted
DESCRIPTION
Read accesses to registers listed below can be corrupted due to
incorrect resynchronization between
clock domains.
Read access to registers below can be corrupted :
•
The series implements work arounds for couple of Erratas.
Tested the series on OMAP5 and DRA7 Boards.
Keerthy (2):
thermal: ti-soc-thermal: dra7: Implement Workaround for Errata i814 -
Bandgap Temperature read Dtemp can be corrupted
thermal: ti-soc-thermal: OMAP5: Implement Workaround
From: Misael Lopez Cruz misael.lo...@ti.com
As per TRM, HDMI_WP_AUDIO_CFG[2] LEFT_BEFORE = 0 is reserved,
so it must always be set to 1 (the first sample is the left).
Signed-off-by: Misael Lopez Cruz misael.lo...@ti.com
Signed-off-by: Jyri Sarha jsa...@ti.com
---
From: Misael Lopez Cruz misael.lo...@ti.com
OMAP4 HDMI IP uses the 8-channel layout with 8-channel speaker
allocation mask when transmitting more than two channels. But
the channel count field (CC) of the Audio InfoFrame's DB1 is
not updated for 8-channels.
As per HDMI Compliance Test 7.31
On Thursday 16 April 2015 03:48 PM, Keerthy wrote:
DESCRIPTION
Spurious Thermal Alert: Talert can happen randomly while the device remains
under the temperature limit
defined for this event to trig. This spurious event is caused by a incorrect
re-synchronization between
clock domains. The
Hi,
On 04/21/2015 03:51 AM, Nishanth Menon wrote:
Alarm interrupt enable register is at offset 0x7, while the time
registers for the alarm follow that. When we program Alarm interrupt
enable prior to programming the time, it is possible that previous
time value could be close or match at the
From: Misael Lopez Cruz misael.lo...@ti.com
DM_INH = 1 (stereo downmix prohibited) and CA = 0x00 (Channel
Allocation: FR, FL) is an invalid combination according to the
HDMI Compliance Test 7.31 Audio InfoFrame.
Signed-off-by: Misael Lopez Cruz misael.lo...@ti.com
Signed-off-by: Jyri Sarha
I have rebased these patches from ti-linux-3.14.y on top of Linux
4.0.0. I tested them briefly on OMAP4 and OMAP5 in my environment, but
I could not test any channel count beyond stereo. However, there were
no conflicts in the rebase and each fix makes sense when looking at
the chip TRM and the
From: Misael Lopez Cruz misael.lo...@ti.com
Downmix inhibit in HDMI_CORE_FC_AUDICONF3 register is in
bit 4 while CEA861_AUDIO_INFOFRAME_DB5_DM_INH sets bit 7.
Signed-off-by: Misael Lopez Cruz misael.lo...@ti.com
Signed-off-by: Jyri Sarha jsa...@ti.com
---
From: Misael Lopez Cruz misael.lo...@ti.com
There is a constraint in the OMAP4 HDMI IP that requires to use
the 8-channel code when transmitting more than two channels.
The constraint doesn't apply for OMAP5 so don't force the channel
allocation in the sound driver as it can be done specifically
On Tue, Apr 21, 2015 at 09:08:53AM -0700, Tony Lindgren wrote:
Looks like omap_gpio_irq_type can return early at several places
leaving a GPIO bank enabled without doing pm_runtime_put if wrong
GPIO arguments are passed.
Instead of adding more complicated BANK_USED macros, let's fix the
* Nishanth Menon n...@ti.com [150421 19:10]:
On 04/21/2015 08:00 PM, Tony Lindgren wrote:
+ /*
+* Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
+* erratum i531 Extra Power Consumed When Repeated Start Operation
+* Mode Is Enabled on I2C Interface
On Wed, Apr 22, 2015 at 04:23:01PM +0300, Jyri Sarha wrote:
From: Misael Lopez Cruz misael.lo...@ti.com
DM_INH = 1 (stereo downmix prohibited) and CA = 0x00 (Channel
Allocation: FR, FL) is an invalid combination according to the
HDMI Compliance Test 7.31 Audio InfoFrame.
Acked-by: Mark
On Wed, Apr 22, 2015 at 04:23:00PM +0300, Jyri Sarha wrote:
From: Misael Lopez Cruz misael.lo...@ti.com
There is a constraint in the OMAP4 HDMI IP that requires to use
the 8-channel code when transmitting more than two channels.
Acked-by: Mark Brown broo...@kernel.org
signature.asc
On 04/22/2015 06:30 AM, Alexandre Belloni wrote:
Apologies on a tardy response, got dragged into another issue and got
cooped up in lab whole day.
On 21/04/2015 at 20:59:15 -0500, Nishanth Menon wrote :
Why is that so? when set alarm is requested for time X, you want
interrupt at time X, not
On Wed, Apr 22, 2015 at 03:42:32PM +0300, Roger Quadros wrote:
So we will have a separate drd fsm file, and the CONFIG_USB_OTG
and CONFIG_USB_OTG_FSM are not needed to be defined, right?
for drd case CONFIG_USB_OTG_FSM is definitely not needed.
I'm not sure if we can operate dual-role
On 04/22/2015 08:26 AM, grygorii.stras...@linaro.org wrote:
Hi,
On 04/21/2015 03:51 AM, Nishanth Menon wrote:
Alarm interrupt enable register is at offset 0x7, while the time
registers for the alarm follow that. When we program Alarm interrupt
enable prior to programming the time, it is
with omap2plus_defconfig on linus master (27cf3a16b253)
and next-20150422
While I do understand that the sleep state and default states are
optional - might be nice to state it in commit message (as a result of
which we dont do error checks).
Would you think adding relevant documentation in
Documentation/devicetree
Hi,
has commit 3b72c2fe0c6bbec42e (drivers: net:ethernet: cpsw: add
support for VLAN) introduced a bug by defining CPSW_VLAN_AWARE as
BIT(1) instead of BIT(2)?
+#define CPSW_VLAN_AWAREBIT(1)
snip
/* switch to vlan unaware mode */
- cpsw_ale_control_set(priv-ale, 0,
On 22/04/15 12:22, Peter Chen wrote:
On Wed, Apr 22, 2015 at 10:33:24AM +0300, Roger Quadros wrote:
On 22/04/15 05:17, Peter Chen wrote:
On Tue, Apr 21, 2015 at 10:34:01AM +0300, Roger Quadros wrote:
On 21/04/15 09:04, Peter Chen wrote:
On 20/04/15 06:05, Peter Chen wrote:
On Tue, Apr
The sDMA controller is capable of performing memory copy operation. It need
to be configured to software triggered mode and without HW synchronization.
The sDMA can copy data which is aligned to 8, 16 or 32 bits.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
drivers/dma/omap-dma.c | 51
On 22/04/15 05:17, Peter Chen wrote:
On Tue, Apr 21, 2015 at 10:34:01AM +0300, Roger Quadros wrote:
On 21/04/15 09:04, Peter Chen wrote:
On 20/04/15 06:05, Peter Chen wrote:
On Tue, Apr 14, 2015 at 01:41:47PM +0300, Roger Quadros wrote:
This is an attempt to centralize OTG/Dual-role
On 04/09/2015 12:35 PM, Peter Ujfalusi wrote:
Vinod: is it OK if I send the Documnetation/dmanegine/ update a bit later when
I have finished it?
Changes since v4:
- Comments from Maxime Ripard addressed:
- long line fixed in of-dma.c
- node leaks has been fixed in ti-dma-crossbar
-
On Fri, Apr 17, 2015 at 05:07:57PM +0200, pascal.hue...@gmail.com wrote:
From: Pascal Huerst pascal.hue...@gmail.com
This adds calls to pinctrl subsystem in order to switch pin states
on suspend/resume if you provide a sleep state in DT.
Signed-off-by: Pascal Huerst pascal.hue...@gmail.com
You are right, the include is missing. I just reapplied the patch,
compiled and interestingly enough, I don't get any compile errors. (?)
I assume you have a different kernel config where something is enabled
which includes the pinctrl-stuff in another include which is included
by these
On 22.04.2015 12:28, Wolfram Sang wrote:
I assume you have a different kernel config where something is enabled
which includes the pinctrl-stuff in another include which is included
by these drivers. Although, my .config was arm-allyesconfig. Can you
send yours?
Sure. See below.
cat
On 21/04/2015 at 20:59:15 -0500, Nishanth Menon wrote :
Why is that so? when set alarm is requested for time X, you want
interrupt at time X, not an interrupt for previous configured RTC
alarm time!
You expect at least an interrupt.
And you will get an interrupt if the event occurs
Hey Wolfram,
On 22.04.2015 10:12, Wolfram Sang wrote:
On Fri, Apr 17, 2015 at 05:07:57PM +0200, pascal.hue...@gmail.com wrote:
From: Pascal Huerst pascal.hue...@gmail.com
This adds calls to pinctrl subsystem in order to switch pin states
on suspend/resume if you provide a sleep state in DT.
From: Pascal Huerst pascal.hue...@gmail.com
This adds calls to pinctrl subsystem in order to switch pin states
on suspend/resume if you provide a sleep state in DT.
Signed-off-by: Pascal Huerst pascal.hue...@gmail.com
---
drivers/i2c/busses/i2c-omap.c | 5 +
1 file changed, 5 insertions(+)
On Wed, Apr 22, 2015 at 10:33:24AM +0300, Roger Quadros wrote:
On 22/04/15 05:17, Peter Chen wrote:
On Tue, Apr 21, 2015 at 10:34:01AM +0300, Roger Quadros wrote:
On 21/04/15 09:04, Peter Chen wrote:
On 20/04/15 06:05, Peter Chen wrote:
On Tue, Apr 14, 2015 at 01:41:47PM +0300,
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