On 07/09/2015 10:15 AM, Sekhar Nori wrote:
> On Thursday 09 July 2015 07:03 AM, Peter Hurley wrote:
[...]
>>> @@ -1307,6 +1320,36 @@ static int omap8250_runtime_suspend(struct device
>>> *dev)
>>> return -EBUSY;
>>> }
>>>
>>> + if (priv->habit & UART_ERRATA_CLOCK_DISA
Here are some basic OMAP test results for Linux v4.2-rc1.
Logs and other details at:
http://www.pwsan.com/omap/testlogs/test_v4.2-rc1/20150705171039/
Test summary
Build: uImage:
Pass ( 3/ 3): omap1_defconfig, omap1_defconfig_1510innovator_only,
omap1_defc
Here are some basic OMAP test results for Linux v4.1.
Logs and other details at:
http://www.pwsan.com/omap/testlogs/test_v4.1/20150626170101/
Test summary
Build: uImage:
Pass ( 3/ 3): omap1_defconfig, omap1_defconfig_1510innovator_only,
omap1_defconfig_59
CONFIG_HAVE_ARM_SCU only gets selected if CONFIG_SMP is selected in an OMAP
system, however AM43XX needs this option regardless of CONFIG_SMP and also
for an AM43XX only build as it is important for controlling power in the SoC.
Without this we cannot suspend the CPU for SoC suspend or cpuidle. The
The OMAP IOMMU driver has been adapted to the IOMMU framework
for a while now, and it no longer supports being built as a
module. Cleanup all the module related references both from
the code and in the build.
While at it, also relocate a comment around the initcall to
avoid a checkpatch strict war
Add missing #iommu-cells property to the DSP and IPU IOMMU nodes
for OMAP5 platforms. This property is required as per the generic
iommu binding.
Signed-off-by: Suman Anna
---
arch/arm/boot/dts/omap5.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/a
Hi Tony,
This series adds the #iommu-cells property to the existing
IOMMU nodes on OMAP4 & OMAP5. It was already fixed for OMAP3
in commit 2055088b5e17 ("ARM: dts: omap3: Add #iommu-cells to
isp and iva iommu").
OMAP4 and OMAP5 do not yet have users for these IOMMUs (remoteproc
nodes), so the war
Add missing #iommu-cells property to the DSP and IPU IOMMU nodes
for OMAP4 platforms. This property is required as per the generic
iommu binding.
Signed-off-by: Suman Anna
---
arch/arm/boot/dts/omap4.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/a
On Thu, Jul 09, 2015 at 09:42:41PM +0200, Wolfram Sang wrote:
> On Thu, Jun 18, 2015 at 12:25:58PM -0500, Felipe Balbi wrote:
> > On Thu, Jun 18, 2015 at 10:09:59AM +0200, Alexander Sverdlin wrote:
> > > Hello Felipe,
> > >
> > > On 17/06/15 21:31, ext Felipe Balbi wrote:
> > > > With this patch w
Hi,
On Thu, Jul 09, 2015 at 09:49:41PM +0200, Wolfram Sang wrote:
> On Thu, Jun 25, 2015 at 02:34:49PM -0500, Felipe Balbi wrote:
> > struct device pointers are usually called
> > dev. Calling our struct omap_i2c_dev pointers
> > also dev has caused enough confusion.
> >
> > This is the result of
Hi Roger,
Thanks for your working.
I'll review, test and apply it on next week because I'm on vacation now.
Thanks,
Chanwoo Choi
On Tue, Jul 7, 2015 at 3:06 PM, Roger Quadros wrote:
> Users of find_cable_index_by_name() will cause a kernel hang
> as the while loop counter is never incremented
On Friday, July 10, 2015 at 05:30:46 PM, Pratyush Anand wrote:
> Hi Kishon,
Hi,
> On Fri, Jul 10, 2015 at 8:19 PM, Kishon Vijay Abraham I
> wrote:
>
> [...]
>
> >> Have you tested with a card having IO space memory as well.
> >
> > I don't have any cards with IO space memory. Do you have any
Hi Kishon,
On Fri, Jul 10, 2015 at 8:19 PM, Kishon Vijay Abraham I wrote:
[...]
>> Have you tested with a card having IO space memory as well.
>
> I don't have any cards with IO space memory. Do you have any suggestion for
> cards with IO space memory?
Sorry, I never used it either :(
IIRC, th
From: Tony Lindgren
We get a NULL pointer dereference on omap3 for thumb2 compiled kernels:
Internal error: Oops: 8005 [#1] SMP THUMB2
...
[] (_raw_spin_unlock_irqrestore) from []
(omap3_enter_idle_bm+0xc5/0x178)
[] (omap3_enter_idle_bm) from []
(cpuidle_enter_state+0x77/0x27c)
[] (cpuidle_e
Hi Felipe,
On Tuesday 07 July 2015 12:30 AM, Felipe Balbi wrote:
> On Wed, Jun 10, 2015 at 02:48:48PM +0530, Kishon Vijay Abraham I wrote:
>> No functional change. Used _roundup_ macro to calculate the transfer
>> size aligned to maxpacket in dwc3_ep0_complete_data. It also makes it
>> similar to
Hi,
On Friday 03 July 2015 05:34 PM, Grygorii Strashko wrote:
> Hi Kishon,
>
> On 07/03/2015 02:03 PM, Kishon Vijay Abraham I wrote:
>> Add PM support to pci-dra7xx so that PCI clocks can be disabled
>> during suspend and enabled back during resume without affecting
>> PCI functionality.
>>
>> Si
Hi Pratyush,
On Friday 10 July 2015 06:52 PM, Pratyush Anand wrote:
> Hi Kishon,
>
> On Fri, Jul 3, 2015 at 4:33 PM, Kishon Vijay Abraham I wrote:
>> Certain platforms require MSE bit to be cleared to set the master
>> in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
>> Controller
Hi Herbert,
On Wednesday 08 July 2015 09:48 AM, Herbert Xu wrote:
> On Tue, Jul 07, 2015 at 09:01:48PM +0530, Lokesh Vutla wrote:
>>
>> +static int omap_aes_gcm_copy_buffers(struct omap_aes_dev *dd,
>> + struct aead_request *req)
[..snip..]
>> +static int do_encryp
Hi Wolfram,
On 07/10/2015 12:09 PM, Wolfram Sang wrote:
>
>> 60 s sounds way too much and actually I simply don't believe this is
>> the root cause. If I take a look into the driver, then I see, that
>
> I agree, this is just a workaround.
>
>> the design is not really the best. The whole IRQ h
On 07/10/2015 04:26 PM, Alexander Sverdlin wrote:
> Hi!
>
> On 10/07/15 15:17, ext Vignesh R wrote:
I would propose you to throw away spinlocks. Convert threaded IRQ to
Agree. Looks like spinlock is not needed.
>> just one hardirq handler. And continue debugging. You will reduce the
>>>
Hi,
On 07/10/2015 06:56 PM, Alexander Sverdlin wrote:
> Hi!
>
> On 10/07/15 15:17, ext Vignesh R wrote:
I would propose you to throw away spinlocks. Convert threaded IRQ to
>> just one hardirq handler. And continue debugging. You will reduce the
>> load of the system with the above m
Hi!
On 10/07/15 15:17, ext Vignesh R wrote:
>>> I would propose you to throw away spinlocks. Convert threaded IRQ to
>>> >> just one hardirq handler. And continue debugging. You will reduce the
>>> >> load of the system with the above measures, maybe it will not happen
>>> >> any more, maybe you'l
Hi Kishon,
On Fri, Jul 3, 2015 at 4:33 PM, Kishon Vijay Abraham I wrote:
> Certain platforms require MSE bit to be cleared to set the master
> in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe
> Controller Master Standby Behavior advises to use the clearing
> of the local MSE bit to
On 07/10/2015 02:39 PM, Wolfram Sang wrote:
>
>> 60 s sounds way too much and actually I simply don't believe this is
>> the root cause. If I take a look into the driver, then I see, that
>
> I agree, this is just a workaround.
>
Yes, this is a workaround. I thought this is simpler change and
Since the Interrupt Events are used only by the NAND driver,
there is no point in managing the Interrupt registers
in the GPMC driver and complicating it with irqchip modeling.
Let's manage the interrupt registers directly in the NAND driver
and get rid of irqchip model from GPMC driver.
Get rid
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 26 ++
1 file changed, 18 insertions
Stop registering driver at postcore and do it
the standard way.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 995e9b8..f19edc2 100644
---
GPMC and NAND drivers share the same register space but never use the
same registers. As there is no clear address seperation between the
registers for GPMC and NAND, we can't easily split it up into 2 regions
i.e. one for GPMC and other for NAND. Instead, we simply remap the entire
register space
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/am335x-baltos-ir5221.dts | 9 +++--
arch/arm/boot/dts/am335x-chilisom.dtsi | 8 ++--
arch/arm/boot/dts/am335x-evm.dts | 8 +
Add compatible id, interrupts and update reg property description.
As the NAND controller needs access to GPMC register space, we need
to pass a second memory resource to the NAND controller node.
Due to the weird way the reg property has been implemented (i.e.
CS number required in 1st number of
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 133 +
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 134 --
include/linux/platform_data/gpmc-omap.h | 139
2 files changed, 139 insertions(
The last register address is offset at 0x2d0 but is a
4 bit register. So total GPMC register resource size
is 0x2d4
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/omap3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/o
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros
---
drivers/memory/om
The write protect (WP) pin is only used for NAND devices. So move
the code into the NAND driver.
Get rid of gpmc_configure() as it is no longer used.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 4
drivers/memory/omap-gpmc.c | 30 --
Hi,
The OMAP GPMC IP is being used on non-OMAP platforms as well
and this series aims at cleaning up device tree implementation
for GPMC NAND so that it can be used on non-OMAP platforms.
NAND is now treated as any other generic GPMC child and has to
have its own compatible-id and address+interru
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30 +
On Wed, Jul 08, 2015 at 01:19:26PM +0300, Roger Quadros wrote:
> Hi,
>
> This series centralizes OTG/Dual-role functionality in the kernel.
> As of now I've got Dual-role functionality working pretty reliably on
> dra7-evm and am437x-gp-evm. xhci side of things for OTG/DRD use are already
> in v4.
On Wed, Jul 08, 2015 at 01:19:28PM +0300, Roger Quadros wrote:
> Move the state_changed variable into struct otg_fsm
> so that we can support multiple instances.
>
I am not sure if multiple instances may happen since OTG protocol requires
only one OTG port can be equipped on OTG device.
Li Jun
> 60 s sounds way too much and actually I simply don't believe this is
> the root cause. If I take a look into the driver, then I see, that
I agree, this is just a workaround.
> the design is not really the best. The whole IRQ handling could be
> actually performed in hard IRQ handler, without t
Hi Vignesh,
On 10/07/15 07:09, ext Vignesh R wrote:
> When system is under load and there is an i2c transaction running
> following warning appears on the console:
>
> [ 730.003617] omap_i2c 4807.i2c: controller timed out
> [ 731.023643] omap_i2c 4807.i2c: controller timed out
>
> This
Vignesh,
On 10/07/15 08:09, Vignesh R wrote:
> When system is under load and there is an i2c transaction running
> following warning appears on the console:
>
> [ 730.003617] omap_i2c 4807.i2c: controller timed out
> [ 731.023643] omap_i2c 4807.i2c: controller timed out
>
> This is bec
On 07/09/2015 11:46 PM, Pavel Machek wrote:
> On Thu 2015-07-09 23:39:22, Pavel Machek wrote:
>> Hi!
Hi,
>>
>> sysfs should contain one value per file. This one has at least two,
>> with nice english sentence as a bonus.
>>
>> root@n900:/sys/devices/platform/6800.ocp/480ab000.usb_otg_hs/musb-
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