* Tony Lindgren [150918 13:27]:
> And also.. It seems wl18xx somehow keeps looing for a wrong
Sorry sent the email before finishing it :) Note related to
these patches, but the wl18xx keeps looking for wrong firmware
and produces the following:
# modprobe wlcore_sdio
...
wlcore: ERROR configura
* Tony Lindgren [150918 10:54]:
> * Javier Martinez Canillas [150918 10:39]:
> > Hello Tony,
> >
> > [snip]
> >
> > >
> > > + vmmcsdio_fixed: fixedregulator-mmcsdio {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "vmmcsdio_fixed";
> > > +
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt
---
Hello,
This patch adds the missing MODULE_DEVICE_TABLE() for OF to export
that information so modules have the correct aliase
On Fri, Sep 18, 2015 at 11:51 AM, Tony Lindgren wrote:
> * Robert Nelson [150918 09:45]:
>> On Fri, Sep 18, 2015 at 11:29 AM, Tony Lindgren wrote:
>> > Commit 99f84cae43df ("ARM: dts: add wl12xx/wl18xx bindings") added
>> > device tree bindings for the TI WLAN SDIO on many omap variants.
>> >
>>
Hi Tony,
This series adds the sub-mailbox nodes and enable them for each
of the TI DRA7 boards. These are the basic mailbox configuration
nodes required by client users (remoteproc) to communicate with
the various IPU and DSP processor devices on DRA74x and DRA72x
SoCs using the TI IPC 3.x softwar
Enable the System Mailboxes 5 and 6 and the corresponding
child sub-mailbox (IPC 3.x) nodes for the DRA7 EVM board.
This is needed to enable communication with the respective
remote processors IPU1, IPU2, DSP1 and DSP2 from the MPU.
Signed-off-by: Suman Anna
---
arch/arm/boot/dts/dra7-evm.dts |
Enable the System Mailboxes 5 and 6 and the corresponding
child sub-mailbox (IPC 3.x) nodes for the DRA72 EVM board.
This is needed to enable communication with the respective
remote processors IPU1, IPU2, and DSP1 from the MPU.
Signed-off-by: Suman Anna
---
arch/arm/boot/dts/dra72-evm.dts | 17
Add the sub-mailbox nodes that are used to communicate between
MPU and the remote processors IPU1, IPU2, DSP1 and DSP2.
The sub-mailbox nodes utilize the System Mailbox instances 5 and 6.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI IPC 3.x sof
Add the sub-mailbox nodes that are used to communicate between
MPU and the remote processors IPU1, IPU2 and DSP1. These match the
respective node definitions on DRA74x to maintain compatibility for
the equivalent remote processors. There is no DSP2 on DRA72x, and
so the corresponding sub-mailbox no
Enable the System Mailboxes 5 and 6 and the corresponding child
sub-mailbox (IPC 3.x) nodes for the Beagle X15 EVM boards. This
is needed to enable communication with the respective remote
processors IPU1, IPU2, DSP1 and DSP2 from the MPU.
Signed-off-by: Suman Anna
---
arch/arm/boot/dts/am57xx-b
* Javier Martinez Canillas [150918 10:39]:
> Hello Tony,
>
> [snip]
>
> >
> > + vmmcsdio_fixed: fixedregulator-mmcsdio {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vmmcsdio_fixed";
> > + regulator-min-microvolt = <180>;
> > +
Hi Grazvydas,
* Tony Lindgren [150908 14:11]:
> * Grazvydas Ignotas [150908 13:44]:
> > On Tue, Sep 8, 2015 at 4:38 PM, Tony Lindgren wrote:
> OK nice to hear you found it. Yeah looks like some runtime
> capability check is needed.
>
> > > Do you have some easy way to reproduce this issue?
>
Hello Tony,
[snip]
>
> + vmmcsdio_fixed: fixedregulator-mmcsdio {
> + compatible = "regulator-fixed";
> + regulator-name = "vmmcsdio_fixed";
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <180>;
> +
* Tony Lindgren [150918 09:55]:
> * Robert Nelson [150918 09:45]:
> > On Fri, Sep 18, 2015 at 11:29 AM, Tony Lindgren wrote:
> > > Commit 99f84cae43df ("ARM: dts: add wl12xx/wl18xx bindings") added
> > > device tree bindings for the TI WLAN SDIO on many omap variants.
> > >
> > > I recall wonder
* Robert Nelson [150918 09:45]:
> On Fri, Sep 18, 2015 at 11:29 AM, Tony Lindgren wrote:
> > Commit 99f84cae43df ("ARM: dts: add wl12xx/wl18xx bindings") added
> > device tree bindings for the TI WLAN SDIO on many omap variants.
> >
> > I recall wondering how come omap5-uevm did not have the WLAN
On Fri, Sep 18, 2015 at 11:29 AM, Tony Lindgren wrote:
> Commit 99f84cae43df ("ARM: dts: add wl12xx/wl18xx bindings") added
> device tree bindings for the TI WLAN SDIO on many omap variants.
>
> I recall wondering how come omap5-uevm did not have the WLAN
> added and this issue has been bugging me
On Fri, Sep 18, 2015 at 09:29:04AM -0700, Tony Lindgren wrote:
> Commit 68bab8662f49 ("mfd: twl6040: Optional clk32k clock handling")
> added clock handling for the 32k clock from palmas-clk. However, that
> patch did not consider a typical situation where twl6040 is built-in,
> and palmas-clk is a
Commit 68bab8662f49 ("mfd: twl6040: Optional clk32k clock handling")
added clock handling for the 32k clock from palmas-clk. However, that
patch did not consider a typical situation where twl6040 is built-in,
and palmas-clk is a loadable module like we have in omap2plus_defconfig.
If palmas-clk is
Commit 99f84cae43df ("ARM: dts: add wl12xx/wl18xx bindings") added
device tree bindings for the TI WLAN SDIO on many omap variants.
I recall wondering how come omap5-uevm did not have the WLAN
added and this issue has been bugging me for a while now, and
I finally tracked it down to a bad pinmux r
Hi all,
Here are two fixes for omap5-uevm WLAN.
Regards,
Tony
Tony Lindgren (2):
mfd: twl6040: Fix deferred probe handling for clk32k
ARM: dts: Fix WLAN regression on omap5-uevm
arch/arm/boot/dts/omap5-uevm.dts | 51 +++-
drivers/mfd/twl6040.c
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 134 ---
include/linux/platform_data/gpmc-omap.h | 137
2 files changed, 137 insertions
Hi,
We do a couple of things in this series which result in
cleaner device tree implementation, faster perfomance and
multi-platform support. As an added bonus we get new GPI/Interrupt pins
for use in the system.
- Establish a custom interface between NAND and GPMC driver. This is
needed because
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 2 --
drivers/mtd/nand/omap2.c | 9 -
include/linux/platform_data/mtd-nand-omap2.h | 4 +++-
3 f
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops->nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drive
Provide functions to enable/disable NAND IRQs, get
NAND event status and clear NAND events.
The NAND events of interest are TERMCOUNT and FIFOEVENT.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 50 ++
include/linux/omap-gpmc.h | 4 +
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index a80c53e..17
The OMAP GPMC module has certain registers dedicated for NAND
access and some NAND bits mixed with other GPMC functionality.
For the NAND dedicated registers we have the struct gpmc_nand_regs.
The NAND driver needs to access NAND specific bits from the
following non-dedicated registers
1) FIFOEVE
Manage NAND interrupts here using the GPMC IRQ ops.
This causes performance in prefetch-irq mode to be increased
from
[ 38.252811] mtd_speedtest: eraseblock write speed is 5576 KiB/s
[ 39.265259] mtd_speedtest: eraseblock read speed is 8192 KiB/s
to
[ 35.666446] mtd_speedtest: eraseblock w
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 26 ++
1 file changed, 18 insertions
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 135 +
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros
---
.../bindings/{bus/ti-gpmc.txt => memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{bus/ti-gpmc.txt =>
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/om
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros
---
drivers/memory/om
Add compatible id and interrupts. The NAND interrupts are
provided by the GPMC controller node.
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bind
The WAIT pins support either rising or falling edge interrupts
so add irqchip support to the gpiochip model.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 132 +
1 file changed, 132 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 130 +
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by:
GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.
They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 2 +-
include/linux/platform_data/mtd-nand-o
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 29 +---
include/linux/platform_dat
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.
Read speed increases from 16516 KiB/ to 18813 KiB/s
and write speed was
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra72-e
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by:
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by:
Make gpmc node gpio+interrupt capable.
Add compatible id, interrupt and wait pin to NAND node.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dm8168-evm.dts | 7 ---
arch/arm/boot/dts/dm816x.dtsi| 4
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/d
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.
Read speed increases from 7869 KiB/ to 8875 KiB/s
and write speed was un
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by:
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c | 163 +-
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30 +
On Tue, Sep 15, 2015 at 06:58:01PM +0530, Lokesh Vutla wrote:
>
> + assoc = &req->src[0];
> + sg_init_table(dd->in_sgl, nsg + 1);
> + if (assoclen) {
> + if (omap_aes_check_aligned(assoc, assoclen)) {
> + dd->sgs_copied |= AES_ASSOC_DATA_COPIED;
> +
On 09/16/2015 04:26 PM, Mark Brown wrote:
> On Wed, Sep 16, 2015 at 03:38:09PM +0530, Vignesh R wrote:
>
>> But, I didn't get how to integrate with existing message queue. Memory
>> mapped read by-passes message queue of SPI core. Could you please
>> explain a bit more on integrating with messag
On 09/11/2015 03:27 PM, Peter Ujfalusi wrote:
> + if (irq >= 0) {
> + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint\n",
The '\n' should not be in the format string.
> + dev_name(dev));
> + ret = devm_request_irq(dev, irq, dm
Register ASoC HDMI codec for audio functionality. This is an initial
ASoC audio implementation for tda998x driver and it does not use all
the features provided by hdmi-codec.
HDMI audio info-frame and audio stream header is generated by the ASoC
HDMI codec. The codec also applies constraints for a
The hdmi-codec is a platform device driver to be registered from
drivers of external HDMI encoders with I2S and/or spdif interface. The
driver in turn registers an ASoC codec for the HDMI encoder's audio
functionality.
The structures and definitions in the API header are mostly redundant
copies of
Changes since RFC v3,
ASoC side:
- Add "ALSA: pcm: add IEC958 channel status helper for hw_params"
- Add "tda998x: Improve tda998x_configure_audio() audio related pdata"
- use snd_pcm_create_iec958_consumer_hw_params() to construct the stream header
- Remove set_clk() callback from hdmi-codec. It i
Add HDMI audio support. Adds mcasp0_pins, clk_mcasp0_fixed,
clk_mcasp0, mcasp0, sound node, and updates the tda19988 node to
follow the new binding.
Signed-off-by: Jyri Sarha
---
arch/arm/boot/dts/am335x-boneblack.dts | 90 --
1 file changed, 86 insertions(+), 4 d
Move struct tda998x_audio definition to tda998x_drv.c and remove
include/sound/tda998x.h. There is no external use for struct
tda998x_audio.
Fix graph parsing to allow ports to be inside a separate "ports"-node as
specified in Documentation/devicetree/bindings/graph.txt.
Signed-off-by: Jyri Sarha
Declare struct tda998x_audio_params in include/drm/i2c/tda998x.h and
use it in pdata and for tda998x_configure_audio() parameters. Also updates
tda998x_write_aif() to use hdmi_audio_infoframe_pack() and friends.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/armada/armada_drv.c | 25 ++--
dr
Add IEC958 channel status helper that gets the audio properties from
snd_pcm_hw_params instead of snd_pcm_runtime. This is needed to
produce the channel status bits already in audio stream configuration
phase.
Signed-off-by: Jyri Sarha
---
include/sound/pcm_iec958.h | 2 ++
sound/core/pcm_iec95
The hdmi stub codec has not been used since refactoring of OMAP HDMI
audio support.
Signed-off-by: Jyri Sarha
---
sound/soc/codecs/Kconfig | 4 --
sound/soc/codecs/Makefile | 2 -
sound/soc/codecs/hdmi.c | 109 --
3 files changed, 115 deletions(
From: Jean-Francois Moine
Two kinds of ports may be declared in a DT graph of ports: video and audio.
This patch accepts the port value from a video port as an alternative
to the video-ports property.
It also accepts audio ports in the case the transmitter is not used as
a slave encoder.
The new
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