On Wed, 2013-03-20 at 13:59 +0530, Santosh Shilimkar wrote:
On Wednesday 20 March 2013 12:12 PM, Sekhar Nori wrote:
I have no clue why my address should bounce.
Me neither.
TI's incoming mail appears to be broken. For days at a time, it is
simply giving a '421 Service Temporarily
On Fri, 2012-07-06 at 11:35 -0300, William F. wrote:
I've requested several times to remove my e-mail from that list. I'll
report it to legal authorities on this issue if no action is taken.
Have you tried following the link at the bottom of every mail you
receive from the list, and following
On Fri, 2011-11-11 at 13:58 +0100, Joerg Roedel wrote:
For AMD IOMMU there is a feature called not-present cache. It says that
the IOMMU caches non-present entries as well and needs an IOTLB flush
when something is mapped (meant for software implementations of the
IOMMU).
So it can't be
On Thu, 2011-11-10 at 14:17 +0800, Kai Huang wrote:
And another question: have we considered the IOTLB flush operation? I
think we need to implement similar logic when flush the DVMA range.
Intel VT-d's manual says software needs to specify the appropriate
mask value to flush large pages, but
On Thu, 2011-11-10 at 18:09 +0100, Joerg Roedel wrote:
The requirement for the DMA-API is, that the IOTLB must be consistent
with existing mappings, and only with the parts that are really mapped.
The unmapped parts are not important.
This allows nice optimizations like your 'batched unmap'
On Tue, 2011-09-13 at 22:31 +0300, Ohad Ben-Cohen wrote:
+ * Traditionally the IOMMU core just handed us the mappings directly,
+ * after making sure the size is an order of a 4KB page and that the
+ * mapping has natural alignment.
+ *
+ * To retain this behavior, we currently advertise that
address space.
I suspect the interrupt remapping support may well want to move with it
too. It's no more out-of-place in drivers/iommu than it is in
drivers/pci. And then you can certainly move dmar.o too.
--
David WoodhouseOpen Source Technology Centre
david.woodho
-by: David Woodhouse david.woodho...@intel.com
Unless you'd prefer me to send it on myself, please feel free to submit
it to Linus directly.
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dwmw2
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On Mon, 2010-10-25 at 11:04 +0530, G, Manjunath Kondaiah wrote:
David,
-Original Message-
From: David Woodhouse [mailto:dw...@infradead.org]
Sent: Monday, October 25, 2010 5:32 AM
To: Menon, Nishanth
Cc: Russell King - ARM Linux; G, Manjunath Kondaiah;
linux-omap
nonsense.
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David WoodhouseOpen Source Technology Centre
david.woodho...@intel.com Intel Corporation
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not to rely on gcc and use
If you ever see gcc screwing up division of an 'int' by a constant 64,
file a GCC bug.
--
David WoodhouseOpen Source Technology Centre
david.woodho...@intel.com Intel Corporation
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