to, 2012-11-01 kello 23:49 +0100, Wolfram Sang kirjoitti:
Hi,
Anyway new patch coming soon :)
Was there one? I have skimmed a number of threads discussing spurious
interrupts or interrupt floods but AFAICS all discussions ended up in
trying another approach later or fixing the issue
ke, 2012-10-17 kello 19:02 +0300, Felipe Balbi kirjoitti:
Hi,
On Thu, Oct 11, 2012 at 02:08:25PM -0700, Kevin Hilman wrote:
Hi Kalle,
Kalle Jokiniemi kalle.jokini...@jollamobile.com writes:
The resume_noirq enables interrupts one-by-one starting from
first one. Now if the wake
Hi,
ma, 2012-10-15 kello 18:02 -0700, Tony Lindgren kirjoitti:
* Kevin Hilman khil...@deeprootsystems.com [121015 10:32]:
Kalle Jokiniemi kalle.jokini...@jollamobile.com writes:
Does not work for me :(
As I said, the issue occurs for me when I enter static suspend (echo mem
/sys
hangs
the device.
Fixed the issue by setting the SIH irqs with IRQF_EARLY_RESUME
flags, so they get enabled before the PIH.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@jollamobile.com
---
drivers/mfd/twl4030-irq.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
Hi,
ti, 2012-10-16 kello 17:59 +0300, Kalle Jokiniemi kirjoitti:
The irqs are enabled one-by-one in pm core resume_noirq phase.
This leads to situation where the twl4030 primary interrupt
handler (PIH) is enabled before the chained secondary handlers
(SIH). As the PIH cannot clear the pending
,
omap_i2c_runtime_resume, NULL)
};
- Grygorii
From: Kevin Hilman [khil...@deeprootsystems.com]
Sent: Friday, October 12, 2012 5:34 PM
To: Strashko, Grygorii
Cc: Kalle Jokiniemi; linux-...@vger.kernel.org; w.s...@pengutronix.de;
ben-li...@fluff.org; t
: for proper sharing the I2C with
a coprocessor, this driver still needs hwspinlock support added.
This change is also meant to address an issue reported by Kalle
Jokiniemi where I2C bus interrupt may be enabled before an I2C device
interrupt handler (e.g. just after noirq resume phase) causing
ma, 2012-10-15 kello 15:41 +0530, Shubhrajyoti Datta kirjoitti:
On Mon, Oct 15, 2012 at 2:46 PM, Kalle Jokiniemi
kalle.jokini...@jollamobile.com wrote:
ma, 2012-10-15 kello 09:21 +0300, Kalle Jokiniemi kirjoitti:
Hi,
pe, 2012-10-12 kello 14:46 +, Strashko, Grygorii kirjoitti:
Hi
To: Kalle Jokiniemi
Cc: linux-...@vger.kernel.org; w.s...@pengutronix.de; ben-li...@fluff.org;
t...@atomide.com; linux-omap@vger.kernel.org; Strashko, Grygorii; Datta,
Shubhrajyoti
Subject: Re: [PATCH v3] ARM: OMAP: i2c: fix interrupt flood during resume
Hi Kalle,
Kalle Jokiniemi
yet.
Fixed the issue by adding suspend_late and resume_early
functions that keep i2c bus interrupts disabled until
resume_noirq has run completely.
Issue was detected doing a wake up from autosleep with
twl4030 power key on N9. Patch tested on N9.
Signed-off-by: Kalle Jokiniemi kalle.jokini
ke, 2012-10-10 kello 14:46 +0300, Kalle Jokiniemi kirjoitti:
The resume_noirq enables interrupts one-by-one starting from
first one. Now if the wake up event for suspend came from i2c
device, the i2c bus irq gets enabled before the threaded
i2c device irq, causing a flood of i2c bus interrupts
yet.
Fixed the issue by adding suspend_noirq and resume_early
functions that keep i2c bus interrupts disabled until
resume_noirq has run completely.
Issue was detected doing a wake up from autosleep with
twl4030 power key on N9. Patch tested on N9.
Signed-off-by: Kalle Jokiniemi kalle.jokini
pe, 2012-10-05 kello 15:07 -0700, Kevin Hilman kirjoitti:
+Grygorii (who's been working on various I2C related suspend/resume
issues also)
Hi Kalle,
Kalle Jokiniemi kalle.jokini...@jollamobile.com writes:
The resume_noirq enables interrupts one-by-one starting from
first
yet.
Fixed the issue by adding suspend_late and resume_early
functions that keep i2c bus interrupts disabled until
resume_noirq has run completely.
Issue was detected doing a wake up from autosleep with
twl4030 power key on N9. Patch tested on N9.
Signed-off-by: Kalle Jokiniemi kalle.jokini
unnecessary vaux2 consumer regulator supply
Kalle Jokiniemi (2):
OMAP3: ISP: Add regulator control for omap34xx
OMAP3: RX-51: define vdds_csib regulator supply
arch/arm/mach-omap2/board-rx51-peripherals.c |6 +
drivers/media/video/omap3isp/ispccp2.c | 27
The RX-51 uses the CSIb IO complex for camera operation. The
board file is missing definition for the regulator supplying
the CSIb complex, so this is added for better power
management.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
arch/arm/mach-omap2/board-rx51-peripherals.c
The current omap3isp driver is missing regulator handling
for CSIb complex in omap34xx based devices. This patch
adds a mechanism for this to the omap3isp driver.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Acked-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
---
drivers
unused regulators.
Also this helps in adding more fine grain regulator
support for rx-51 in the future.
Thanks for Mark Brown for pointing out the correct
solution.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Cc: Mark Brown broo...@opensource.wolfsonmicro.com
---
arch/arm/mach-omap2
Nikula and Mark Brown.
Kalle Jokiniemi (1):
OMAP3: rx-51: Add full regulator definitions
arch/arm/mach-omap2/board-rx51-peripherals.c | 69 ++
1 files changed, 69 insertions(+), 0 deletions(-)
--
To unsubscribe from this list: send the line unsubscribe linux-omap
The current omap3isp driver is missing regulator handling
for CSIb complex in omap34xx based devices. This patch
adds a mechanism for this to the omap3isp driver.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
drivers/media/video/omap3isp/ispccp2.c | 27
Laurent Pinchart
Kalle Jokiniemi (2):
OMAP3: ISP: Add regulator control for omap34xx
OMAP3: RX-51: define vdds_csib regulator supply
arch/arm/mach-omap2/board-rx51-peripherals.c |9
drivers/media/video/omap3isp/ispccp2.c | 27 -
drivers/media/video
The RX-51 uses the CSIb IO complex for camera operation. The
board file is missing definition for the regulator supplying
the CSIb complex, so this is added for better power
management.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
arch/arm/mach-omap2/board-rx51-peripherals.c
, since most
of the changes are on the omap3isp driver side.
Any comments/review appreciated. Tested on Nokia N900 and the
MeeGo testing daily images (.37 based kernel). Patches on top
of Mauro's linux-next tree, build tested and boot tested with
that.
Kalle Jokiniemi (2):
OMAP3: ISP: Add
The current omap3isp driver is missing regulator handling
for CSIb complex in omap34xx based devices. This patch
adds a mechanism for this to the omap3isp driver.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
drivers/media/video/omap3isp/ispccp2.c | 24
The RX-51 uses the CSIb IO complex for camera operation. The
board file is missing definition for the regulator supplying
the CSIb complex, so this is added for better power
management.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
arch/arm/mach-omap2/board-rx51-peripherals.c
unused regulators.
Also this helps in adding more fine grain regulator
support for rx-51 in the future.
Thanks for Mark Brown for pointing out the correct
solution.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Cc: Mark Brown broo...@opensource.wolfsonmicro.com
---
arch/arm/mach-omap2
Adding regulator definitions to correctly shut down unneeded
regulators. Needed, but previously undefined regulators were
marked always_on.
Tested on top of MeeGo N900 DE daily release (.37 kernel) and
with linux-omap. Patch based on linux-omap HEAD.
Kalle Jokiniemi (1):
OMAP3: rx-51: Add full
to WARN_ON
* editorial fixes
v2: fixed boot issue in the 1/2 patch.
Kalle Jokiniemi (2):
isp1704_charger: allow board specific powering routine
RX-51: Enable isp1704 power on/off
arch/arm/mach-omap2/board-rx51-peripherals.c | 27 ++-
drivers/power/isp1704_charger.c
to Heikki Krogerus for helping out with the patch.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Cc: Heikki Krogerus heikki.kroge...@nokia.com
---
drivers/power/isp1704_charger.c | 22 ++
include/linux/power/isp1704_charger.h | 29
patch since the indent fix is only needed
when there are multiple members in the struct definition.
Loosely based on earlier patches from Heikki Krogerus in
Nokia N900 maemo kernel.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Cc: Heikki Krogerus heikki.kroge...@nokia.com
---
arch
This patch set enables powering down the isp1704 usb
tranceiver when not in use.
Tested on RX-51.
Kalle Jokiniemi (2):
isp1704_charger: allow board specific powering routine
RX-51: Enable isp1704 power on/off
arch/arm/mach-omap2/board-rx51-peripherals.c | 27
to Heikki Krogerus for helping out with the patch.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Cc: Heikki Krogerus heikki.kroge...@nokia.com
---
drivers/power/isp1704_charger.c | 23 +++
include/linux/power/isp1704_charger.h | 29
to Heikki Krogerus for helping out with the patch.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Cc: Heikki Krogerus heikki.kroge...@nokia.com
---
drivers/power/isp1704_charger.c | 26 ++
include/linux/power/isp1704_charger.h | 29
The isp1704 usb tranceiver is used for charging and can be
disabled when not in use. Provide the powering routine to
the driver via platform data.
Loosely based on earlier patches from Heikki Krogerus in
Nokia N900 maemo kernel.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Cc: Heikki
This patch set enables powering down the isp1704 usb
tranceiver when not in use.
Tested on RX-51 and MeeGo.
v2: fixed a boot issue in the 1/2 patch.
Kalle Jokiniemi (2):
isp1704_charger: allow board specific powering routine
RX-51: Enable isp1704 power on/off
arch/arm/mach-omap2/board
.
Basic test done on MeeGo + linux usb that the ISP powering
happens correctly. Also simple data transfer tests done with
backported patches on MeeGo n900 kernel.
Cross posting to linux-omap, but I propose that we'd push these
to linux-usb. Patches based on linux-usb master.
Kalle Jokiniemi (2
In case some board has special powering sequences for
the USB tranceiver, call those during __twl4030_phy_power
calls.
This is a preparation patch to allow powering down the
ISP1707 USB serial tranceiver in Nokia N900.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
drivers/usb/otg
The smart idle mode in wdtimer2 prevents CORE power domain
idle transitions. Disable SMART idle mode to allow
FORCE idle mode to be used.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |7 +--
1 files changed, 5 insertions(+), 2
and select in following priority:
1. Smart idle mode
2. Force idle mode
3. No idle mode.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
arch/arm/mach-omap2/omap_hwmod.c | 28
1 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-omap2
From: Paul Walmsley p...@pwsan.com
The HW superwised smart idle for wdtimer in OMAP3 prevents
CORE power domain idle transitions. Disable it by swithing
to SW supervised transitions.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Signed-off-by: Paul Walmsley p...@pwsan.com
---
arch
Walmsley p...@pwsan.com
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
Tested-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
drivers/watchdog/omap_wdt.c | 25 +++--
1 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/watchdog/omap_wdt.c b/drivers
These patches fix the issue where the wdtimer blocks CORE idle
transitions on n900 (OMAP3). The root cause was that SMART idle
mode in wdtimer did not allow the CORE idle transition to happen.
Paul, I added your S-o-bs to the patches already. Please check
that they are ok by you.
Paul Walmsley
These patches fix the issue where the wdtimer blocks CORE idle
transitions on n900 (OMAP3). The root cause was that SMART idle
mode in wdtimer did not allow the CORE idle transition to happen.
v2: updated commit message on patch 1/2, Cc'd Wim, and added
comments to code about possible HW bug in
From: Paul Walmsley p...@pwsan.com
The HW superwised smart idle for wdtimer in OMAP3 prevents
CORE power domain idle transitions. Disable it by swithing
to SW supervised transitions.
This could be a hardware bug in the OMAP3 wdtimer2 block.
Signed-off-by: Kalle Jokiniemi kalle.jokini
From: Paul Walmsley p...@pwsan.com
The omap_wdt should only be in full active state when the
registers are being accessed. Otherwise the device can be
on lower power mode.
This patch is based on a patch created by Kalle Jokiniemi:
https://patchwork.kernel.org/patch/618231/
which is itself based
how to fix this with runtime_pm,
feel free to propose patches. Otherwise I suggest we revert
back to something that works.
Tested with RX-51 S4.0 Macroboard, linux-omap-pm/pm branch and
MeeGo armv7l release.
Kalle Jokiniemi (2):
Revert OMAP: WDT: Use PM runtime APIs instead of clk FW APIs
interface clock always
remaining on when the watchdog is active.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@nokia.com
---
drivers/watchdog/omap_wdt.c | 42 +++---
1 files changed, 35 insertions(+), 7 deletions(-)
diff --git a/drivers/watchdog/omap_wdt.c b
Keeping the omap watchdog interface clock always enabled
blocks OMAP CORE power domain from sleeping. Introduce
fine grain clock control to fix the issue.
This patch is based on a patch created by Atal
Shargorodsky: http://lkml.org/lkml/2009/3/10/266.
Signed-off-by: Kalle Jokiniemi kalle.jokini
From: ext Kalle Jokiniemi kalle.jokini...@digia.com
While waiting for completion of the i2c transfer, the
MPU could hit OFF mode and cause several msecs of
delay that made i2c transfers fail more often. The
extra delays and subsequent re-trys cause i2c clocks
to be active more often. This has
Hi Kevin,
On Fri, 2009-10-30 at 01:07 +0200, Kevin Hilman wrote:
Kalle Jokiniemi kalle.jokini...@digia.com writes:
From: Kalle Jokiniemi ext-kalle.jokini...@nokia.com
The biggest source of latency in idle loop (omap_sram_idle
function) comes from updating the state counters for each
From: Kalle Jokiniemi ext-kalle.jokini...@nokia.com
The biggest source of latency in idle loop (omap_sram_idle
function) comes from updating the state counters for each
power domain. The two purposes of these counters are to
provide debug data in debugfs, and to keep track of context
losses
On Fri, 2009-10-30 at 13:26 +0200, Kalle Jokiniemi wrote:
From: Kalle Jokiniemi ext-kalle.jokini...@nokia.com
The biggest source of latency in idle loop (omap_sram_idle
function) comes from updating the state counters for each
power domain. The two purposes of these counters are to
provide
Hi Kevin,
Made some patches to enable setting RX-51 cpu idle parameters
as we use them. Added valid field passing to cpuidle_params
in the process.
Tested on RX-51. Applies on top of linux-omap/pm branch.
Kalle Jokiniemi (3):
OMAP:PM: Fix non-cpu idle builds using omap3_pm_init_cpuidle
Building without CONFIG_CPU_IDLE causes build to fail if
cpu idle parameters are tried to pass using
omap3_pm_init_cpuidle function.
Fixed by defining a dummy function for non-cpu idle
builds.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/pm.h |7
for each board.
So added the valid field to cpuidle_params and added
support to 3430sdp, which uses the paramenter passing.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/board-3430sdp.c | 14 ++--
arch/arm/mach-omap2/cpuidle34xx.c | 37
OK, let's try this once more, since my mail did not seem to go to
linux-omap.
Sorry for the spam.
See my comments below:
On Fri, 2009-10-23 at 18:53 +0300, Sonasath, Moiz wrote:
Hello Jokiniemi!
-Original Message-
From: Kalle Jokiniemi [mailto:kalle.jokini...@digia.com]
Sent
Hi Kevin,
On Wed, 2009-10-21 at 14:51 +0300, Kalle Jokiniemi wrote:
Hello,
Here are some fruits from digging out the latency sources
of our idle loop. The main latency source was powerdomain
state counter updating at beginning and end of the idle
loop. Also PER previous state reading
According to measurements, reading the previous state of PER
domain after wfi takes ~11us on OPP2.
Removed this unneccessary latency from cases where we know
PER power domain did not try to enter off mode.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/pm34xx.c
-51.
Kalle Jokiniemi (3):
OMAP3: Only update pm-counters when needed
PM: Skip PER previous state register read
OMAP: I2C: Add mpu wake up latency constraint in i2c
arch/arm/mach-omap2/pm-debug.c | 51 -
arch/arm/mach-omap2/pm.h |2
From: Kalle Jokiniemi ext-kalle.jokini...@nokia.com
The biggest source of latency in idle loop (omap_sram_idle
function) comes from updating the state counters for each
power domain. The two purposes of these counters are to
provide debug data in debugfs, and to keep track of context
losses
Hi,
On Mon, 2009-10-05 at 20:08 +0300, Pandita, Vikram wrote:
Jokiniemi
-Original Message-
From: linux-omap-ow...@vger.kernel.org
[mailto:linux-omap-ow...@vger.kernel.org] On Behalf Of Kalle
Jokiniemi
Sent: Thursday, September 17, 2009 11:29 AM
To: khil...@deeprootsystems.com
, and pass them instead.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/plat-omap/i2c.c | 54 +++-
drivers/i2c/busses/i2c-omap.c | 19 +++---
include/linux/i2c-omap.h |9 +++
3 files changed, 66 insertions(+), 16
On Thu, 2009-10-01 at 14:41 +0300, Aaro Koskinen wrote:
Hello,
Kalle Jokiniemi wrote:
On Wed, 2009-09-30 at 19:36 +0300, Kevin Hilman wrote:
Seems like the latency value should also be (optionally) passed in
pdata so this can be experimented with per-platform.
Well, it kind
, and pass them instead.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/plat-omap/i2c.c | 54 +++-
drivers/i2c/busses/i2c-omap.c | 19 +++---
include/linux/i2c-omap.h |9 +++
3 files changed, 66 insertions(+), 16
rx51_defconfig and omap3_pm_defconfig
builds).
Applies on top of pm-branch.
- Kalle
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/plat-omap/i2c.c | 54 +++-
drivers/i2c/busses/i2c-omap.c | 19 +++---
include/linux/i2c
On Thu, 2009-10-01 at 09:10 +0300, Jarkko Nikula wrote:
Hi Kalle
Few minor comments below.
On Thu, 17 Sep 2009 19:28:43 +0300
Kalle Jokiniemi kalle.jokini...@digia.com wrote:
-static u32 i2c_rate[ARRAY_SIZE(i2c_resources)];
+static struct omap_i2c_bus_platform_data
i2c_pdata
Sending this patch that fixes a problem where I2C transfers get stalled
because MPU can hit off mode while i2c is waiting for transfer
completion.
There are some changes on how clkrate is passed to i2c-omap bus
driver, as I needed to pass also the constraint setting function.
So review comments
a constraint that allows MPU to wake up in few
hundred usecs, which is roughly the average i2c wait
period.
The constraint function is passed as platform data from
plat-omap/i2c.c and applied only on OMAP34XX devices.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/plat-omap
mode
state counter, as it could result in a driver not
noticing a context loss.
Fixed by disabling hw supported state transitions
when autodeps are being changed.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/clockdomain.c | 74
On Wed, 2009-09-16 at 15:07 +0300, Tommi Rantala wrote:
2009/9/16 Kalle Jokiniemi kalle.jokini...@digia.com:
There is a possible race condition in clockdomain
code handling hw supported idle transitions.
When multiple autodeps dependencies are being added
or removed, a transition
mode
state counter, as it could result in a driver not
noticing a context loss.
Fixed by disabling hw supported state transitions
when autodeps are being changed.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/clockdomain.c | 74
On Fri, 2009-08-07 at 01:14 +0300, Kevin Hilman wrote:
Roger Quadros ext-roger.quad...@nokia.com writes:
As per errata 1.142, on EMU/HS devices, SDRC_POWER should be programmed
for automatic self-refresh before transition to OFF mode.
In the current implementation this is done in
On Fri, 2009-08-07 at 11:03 +0300, Roger Quadros wrote:
ext Kalle Jokiniemi wrote:
On Fri, 2009-08-07 at 01:14 +0300, Kevin Hilman wrote:
Roger Quadros ext-roger.quad...@nokia.com writes:
As per errata 1.142, on EMU/HS devices, SDRC_POWER should be programmed
for automatic self-refresh
On Fri, 2009-08-07 at 11:48 +0300, Roger Quadros wrote:
ext Kalle Jokiniemi wrote:
On Fri, 2009-08-07 at 11:03 +0300, Roger Quadros wrote:
ext Kalle Jokiniemi wrote:
On Fri, 2009-08-07 at 01:14 +0300, Kevin Hilman wrote:
Roger Quadros ext-roger.quad...@nokia.com writes:
As per errata
On Fri, 2009-08-07 at 13:54 +0300, Roger Quadros wrote:
ext Kalle Jokiniemi wrote:
On Fri, 2009-08-07 at 11:48 +0300, Roger Quadros wrote:
ext Kalle Jokiniemi wrote:
On Fri, 2009-08-07 at 11:03 +0300, Roger Quadros wrote:
ext Kalle Jokiniemi wrote:
On Fri, 2009-08-07 at 01:14 +0300
On Wed, 2009-06-17 at 12:50 +0300, Nayak, Rajendra wrote:
-Original Message-
From: Kalle Jokiniemi [mailto:kalle.jokini...@digia.com]
Sent: Wednesday, June 17, 2009 1:17 PM
To: Nayak, Rajendra
Cc: linux-omap@vger.kernel.org; Derrick, David; Woodruff, Richard
Subject: Re: [PATCH 01
On Wed, 2009-06-17 at 15:38 +0300, Nayak, Rajendra wrote:
-Original Message-
From: Kalle Jokiniemi [mailto:kalle.jokini...@digia.com]
Sent: Wednesday, June 17, 2009 3:56 PM
To: Nayak, Rajendra
Cc: linux-omap@vger.kernel.org; Derrick, David; Woodruff, Richard
Subject: RE: [PATCH 01
On Thu, 2009-05-14 at 18:57 +0300, Kevin Hilman wrote:
Kalle,
In your Enable IO-CHAIN wakeup patch[1], you set a timout based on
1000 tries of reading back from PM_WKST_WKUP.
Just curious how you came up with that value.
I tested it around a few times, and the loop seemed to run 2
On Thu, 2009-05-14 at 20:40 +0300, Woodruff, Richard wrote:
From: Kevin Hilman [mailto:khil...@deeprootsystems.com]
Sent: Thursday, May 14, 2009 12:10 PM
To: Kalle Jokiniemi
Kalle Jokiniemi kalle.jokini...@digia.com writes:
The hardware SAVEANDRESTORE mechanism seems to leave
USB
On Fri, 2009-05-15 at 14:47 +0300, Woodruff, Richard wrote:
couple errata impacting different chip revs.
Today in the older TI reference code this condition of a stuck on
power domain does not happen. However, we are using a software
supervised method to disable the power domain.
The CM_CLKEN_PLL_IVA2 register was not being saved by the
current prcm save/restore code. This patch adds the proper
save/restore for that register.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/prcm.c |5 +
1 files changed, 5 insertions(+), 0 deletions
SMS_SYSCONFIG register gets reset in off mode, added
a save/restore mechanism for that.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/pm34xx.c |1 +
arch/arm/mach-omap2/sdrc.c | 27 +++
arch/arm/plat-omap
period of wrong
clock settings in CM_CLKEN_PLL remained between ROM
code and prcm context restore. This is fixed by the
patch.
Problem reported by: Jouni Högander jouni.hogan...@nokia.com
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/control.c |2 +-
1 files
Following patch should apply on top of pm-branch. Build tested for rx-51.
Kalle Jokiniemi (1):
ARM:OMAP3: Fix PLL_MOD CLKEN offset in scratchpad
arch/arm/mach-omap2/control.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
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Found this chip init problem while debugging a problem with
usb host getting stuck at active mode when toggling the
/sys/power/enable_off_mode. The OMAP_CHIP_INIT calls used
is ES2.0 macros, while it should be now according to the new
macro definitions greater or equal to ES2.0.
Boot tested on
Some modules have been specified only to exist in ES2.0
devices while they should exist on = ES2.0 devices.
Fixed OMAP_CHIP_INIT() calls to take this to account.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/omapdev3xxx.h |8
arch/arm/mach-omap2
On Thu, 2009-04-23 at 12:43 +0300, Kalle Jokiniemi wrote:
Found this chip init problem while debugging a problem with
usb host getting stuck at active mode when toggling the
BTW, this usb host problem is not fixed by this chip init patch. I'm
sending a separate patch that completely disables
The hardware SAVEANDRESTORE mechanism seems to leave
USB HOST power domain permanently into active state
after one transition from off to active state.
Disabling for now.
Signed-off-by: Kalle Jokiniemi ext-kalle.jokini...@nokia.com
---
arch/arm/mach-omap2/powerdomains34xx.h |8 +++-
1
.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/prm-regbits-34xx.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h
b/arch/arm/mach-omap2/prm-regbits-34xx.h
index d73eee8..d792c29 100644
--- a/arch/arm/mach
setting up wrong bits in
PM_PWSTCTRL registers.
Kalle Jokiniemi (1):
ARM: OMAP3: Fix HW SAVEANDRESTORE shift define
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Here's a set of patches to fix some off mode problems in ES3.0 and
ES3.1 devices. Should apply on top of pm branch.
Kalle Jokiniemi (3):
ARM:OMAP3: Enable SDRC workaround for ES3.1
ARM: OMAP3: Fix secure sram saving
ARM: OMAP3: Enable IO-CHAIN wakeup
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to be corrupted, but also left DMA channels in secure mode.
The secure mode DMA channels caused DMA secure error with
device 0 errors to be displayed.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
Signed-off-by: Jouni Hogander jouni.hogan...@nokia.com
---
arch/arm/mach-omap2/pm34xx.c|3
OMAP 3430 ES3.1 chips have a separate bit for IO daisy-chain
wake up enabling. It needs to be enabled when entering
retention or off state, otherwise waking up might not work
in all situations.
Signed-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
arch/arm/mach-omap2/pm34xx.c
On Thu, 2009-02-26 at 14:40 -0800, David Brownell wrote:
On Thursday 26 February 2009, Liam Girdwood wrote:
On Sun, 2009-02-08 at 10:52 -0800, David Brownell wrote:
From: Kalle Jokiniemi kalle.jokini...@digia.com
This patch disables LDO regulators VUSB1V5, VUSB1V8, and VUSB3V1
when
On Fri, 2009-02-13 at 14:35 -0800, David Brownell wrote:
On Friday 13 February 2009, Kalle Jokiniemi wrote:
I ran into some trouble with the merged fix. For some reason clearing
the VUSB3V1_DEV_GRP register causes VUSB_DEDICATED2.VUSB3V1_SLEEP bit to
be enabled. This means that once
-off-by: Kalle Jokiniemi kalle.jokini...@digia.com
---
drivers/usb/otg/Kconfig |2 +-
drivers/usb/otg/twl4030-usb.c | 73 -
2 files changed, 65 insertions(+), 10 deletions(-)
diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
index
This patch combines the two patches TWL: USB: disable VUSB
regulators when cable unplugged and USB: OTG: Twl4030 depends
on REGULATOR_TWL4030 sent earlier by me.
New thing is that the patch now handles situations where
disabling of VUSB3V1 regulator resets the ACTIVE state
remapping to SLEEP to
On Wed, 2009-02-11 at 12:47 +0200, Kalle Jokiniemi wrote:
On Tue, 2009-02-10 at 23:23 -0800, David Brownell wrote:
On Tuesday 10 February 2009, Kalle Jokiniemi wrote:
These couple of patches enable dynamic swithcing of the
regulators used by twl4030 usb tranceiver.
This set
On Tue, 2009-02-10 at 23:23 -0800, David Brownell wrote:
On Tuesday 10 February 2009, Kalle Jokiniemi wrote:
These couple of patches enable dynamic swithcing of the
regulators used by twl4030 usb tranceiver.
This set replaces the single patch USB: disable twl4030
USB regulators when
On Sun, 2009-02-08 at 10:52 -0800, David Brownell wrote:
From: Kalle Jokiniemi kalle.jokini...@digia.com
This patch disables LDO regulators VUSB1V5, VUSB1V8, and VUSB3V1
when the USB cable is unplugged, to eliminate that source of power
waste. (Enabled LDOs consume power at all times
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