On Thu, May 31, 2012 at 3:39 AM, Kevin Hilman khil...@ti.com wrote:
Menon, Nishanth n...@ti.com writes:
On Wed, May 30, 2012 at 12:59 PM, Kevin Hilman khil...@ti.com wrote:
Menon, Nishanth n...@ti.com writes:
On Thu, May 17, 2012 at 3:52 AM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote
On Fri, May 25, 2012 at 1:55 PM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Most of the OMAP4 control module register defines are not used and
can be removed. Keep only needed defines and move them to common
control module header just like
On Fri, May 25, 2012 at 1:55 PM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
This patch exposes the definitions under control.h to
drivers outside the machine code.
Signed-off-by: Eduardo Valentin eduardo.valen...@ti.com
---
After second thought, this complete header movement needs to
On Fri, May 25, 2012 at 1:56 PM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
This patch exposes OMAP4 thermal sensor as a thermal zone
named cpu. Only thermal creation is done here.
TODO:
- Add cooling bindings
- Add extrapolation rules
Signed-off-by: Eduardo Valentin
On Fri, May 25, 2012 at 1:55 PM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
This patch introduces a MFD core device driver for
OMAP system control module.
The control module allows software control of
various static modes supported by the device. It is
composed of two control
On Fri, May 25, 2012 at 1:55 PM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
This is a way to add an early device for system control module.
the code is also requesting for driver registration and probing.
Done at early_initcall because at that time, ioremapping is possible.
On Fri, May 25, 2012 at 6:23 PM, Cousson, Benoit b-cous...@ti.com wrote:
Hi Eduardo,
On 5/25/2012 10:25 AM, Eduardo Valentin wrote:
OMAP system control module can be probed early, then
omap_type is safe to use its APIs.
TODO: add support for other omap versions
Signed-off-by: Eduardo
On Fri, May 25, 2012 at 1:55 PM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
OMAP4460 specific temperature sensor register bit fields are added.
Existing OMAP4 entries are renamed to OMAP4430.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Eduardo Valentin eduardo.valen...@ti.com
On Mon, May 28, 2012 at 5:12 PM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
Hello,
On Mon, May 28, 2012 at 03:24:01PM +0530, Shilimkar, Santosh wrote:
On Fri, May 25, 2012 at 1:55 PM, Eduardo Valentin
eduardo.valen...@ti.com wrote:
This patch introduces a MFD core device driver
On Mon, May 21, 2012 at 3:05 PM, Tero Kristo t-kri...@ti.com wrote:
On Wed, 2012-05-16 at 18:17 -0600, Paul Walmsley wrote:
Hi Tero
On Mon, 14 May 2012, Tero Kristo wrote:
save_secure_all needs l3_main_3_ick and l4_secure_clkdm enabled,
otherwise the secure ROM code will crash.
Do we
On Mon, May 21, 2012 at 3:08 PM, Tero Kristo t-kri...@ti.com wrote:
On Wed, 2012-05-16 at 17:06 -0700, Kevin Hilman wrote:
+Benoit
Tero Kristo t-kri...@ti.com writes:
save_secure_all needs l3_main_3_ick and l4_secure_clkdm enabled,
otherwise the secure ROM code will crash.
Tero,
On Mon, May 21, 2012 at 3:51 PM, Tero Kristo t-kri...@ti.com wrote:
On Wed, 2012-05-16 at 17:31 -0700, Kevin Hilman wrote:
Tero Kristo t-kri...@ti.com writes:
If AUX_CORE_BOOT0 does not indicate wakeup request for cpu1, put it back
to off.
Why is it waking up then? (I know the
Jean,
On Mon, May 21, 2012 at 7:23 PM, Jean Pihet jean.pi...@newoldbits.com wrote:
Hi Santosh,
On Thu, May 17, 2012 at 12:04 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Jean,
On Tuesday 08 May 2012 02:10 PM, Jean Pihet wrote:
Paul,
On Mon, May 7, 2012 at 11:28 AM, Paul Walmsley
On Thu, May 17, 2012 at 10:45 PM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Wed, May 16, 2012 at 10:21 PM, Kevin Hilman khil...@ti.com wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh
On Fri, May 18, 2012 at 5:26 AM, Kevin Hilman khil...@ti.com wrote:
Tony Lindgren t...@atomide.com writes:
* Kevin Hilman khil...@ti.com [120517 15:29]:
I just noticed that this patch has caused some strange problems, notably
with the GPIO IRQ used by smsc911x NIC (Overo, Zoom3, 2430SDP,
+ Afzal who has been doing quite a bit of GMPC work recently.
On Fri, May 18, 2012 at 10:13 AM, Ming Lei ming@canonical.com wrote:
The IRQ52 on OMAP2+ is not a shared interrupt line. If IRQF_SHARED
is passed to request_irq and dev_id is set as NULL, request_irq will
return -EINVAL.
GPMC
On Fri, May 18, 2012 at 12:46 PM, Mohammed, Afzal af...@ti.com wrote:
Hi Santosh,
On Fri, May 18, 2012 at 12:33:16, Shilimkar, Santosh wrote:
+ Afzal who has been doing quite a bit of GMPC work recently.
On Fri, May 18, 2012 at 10:13 AM, Ming Lei ming@canonical.com wrote:
The IRQ52
On Fri, May 18, 2012 at 1:10 PM, Ming Lei ming@canonical.com wrote:
Hi,
On Fri, May 18, 2012 at 3:19 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
:
Are you sure it fails ?
[ 1.778930] GPMC revision 6.0
[ 1.782226] gpmc: irq-52 could not claim: err -22
Afzal pointed me
On Fri, May 18, 2012 at 2:34 PM, Ming Lei ming@canonical.com wrote:
On Fri, May 18, 2012 at 3:43 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
Is the gpmc a shared interrupt line? SHARED is not needed at all for
non shared interrupt line in hardware.
The line is shared.
If so
On Fri, May 18, 2012 at 4:21 PM, Mohammed, Afzal af...@ti.com wrote:
Hi Santosh,
On Fri, May 18, 2012 at 15:43:31, Shilimkar, Santosh wrote:
On the side note, looks like GMPC too needs to be converted
to sparse IRQ since it seems to be creating a dummy irqchip
and dispatching secondary
On Wed, May 16, 2012 at 10:21 PM, Kevin Hilman khil...@ti.com wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
Kevin,
On Wednesday 16 May 2012 02:46 PM, Santosh Shilimkar wrote:
On Wednesday 16 May 2012 03:14 AM, Kevin Hilman wrote:
Santosh,
Tero Kristo t-kri...@ti.com writes:
On Thu, May 17, 2012 at 4:35 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG is when MPU Domain OFF wake up sequence that can compromise
IVA and Tesla execution.
At wakeup from MPU OFF on HS device only
On Thu, May 17, 2012 at 4:47 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
On HS devices on the way out of MPU OSWR and OFF ROM code wrongly
overwrites the CM L3INSTR registers. So to avoid this, save them and
restore on the
On Thu, May 17, 2012 at 4:28 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The SAR RAM is maintained during Device OFF mode.
so why is this patch bothering to save and restore it?
SAR RAM is maintained(not
On Thu, May 17, 2012 at 4:12 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
SAR/ROM code restores only CORE DPLL to its original state
post wakeup from OFF mode.
The rest of the DPLL's in OMAP4 platform (MPU/IVA/ABE/USB/PER)
On Thu, May 17, 2012 at 4:18 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
Restore all CM1/2 module registers as they are lost in OFF mode.
Save and restore?
Also, as in the previous patch. Can this be done using cluster PM
On Thu, May 17, 2012 at 4:06 AM, Kevin Hilman khil...@ti.com wrote:
+Jean for functional power states
Tero Kristo t-kri...@ti.com writes:
This patch adds device off support to OMAP4 device type.
Description is rather thin for a patch that is doing so much.
OFF mode is disabled by default,
On Thu, May 17, 2012 at 5:45 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
Transition When CS1 Is Used On EMIF which impacts OMAP443x silicon
The
On Thu, May 17, 2012 at 12:34 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, May 17, 2012 at 4:12 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Rajendra Nayak rna...@ti.com
SAR/ROM code restores only CORE DPLL to its original state
post
On Thu, May 17, 2012 at 10:12 PM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 4:28 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The SAR RAM
On Thu, May 17, 2012 at 10:15 PM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 4:35 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
The ROM BUG
On Thu, May 17, 2012 at 10:17 PM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Thu, May 17, 2012 at 5:45 AM, Kevin Hilman khil...@ti.com wrote:
Tero Kristo t-kri...@ti.com writes:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around
On Tue, May 15, 2012 at 8:10 PM, Cousson, Benoit b-cous...@ti.com wrote:
Hi Jon,
On 5/15/2012 4:33 PM, Jon Hunter wrote:
Hi Santosh, Benoit,
On 05/10/2012 01:54 AM, Santosh Shilimkar wrote:
On Thursday 10 May 2012 03:06 AM, Jon Hunter wrote:
From: Jon Hunterjon-hun...@ti.com
For
On Tue, May 15, 2012 at 8:02 PM, Cousson, Benoit b-cous...@ti.com wrote:
+ Paul
Hi Tarun,
On 5/15/2012 1:42 PM, Tarun Kanti DebBarma wrote:
Commit 68523f4233de5f233478dde0a63047b4efb710b8 (ARM: OMAP4:
Workaround the OCP synchronisation issue with 32K synctimer)
does not include GP Timers
On Fri, May 11, 2012 at 11:32 AM, Vaibhav Hiremath hvaib...@ti.com wrote:
From: Kevin Hilman khil...@ti.com
There are certain fields inside 'struct dpll_data' which are
included under ARCH_OMAP3 and ARCH_OMAP4 option, which makes it
difficult to use it for new devices like, am33xx, ti81xx,
Jon,
On Thu, May 10, 2012 at 3:03 AM, Jon Hunter jon-hun...@ti.com wrote:
From: Jon Hunter jon-hun...@ti.com
This series adds PMU support for OMAP4 devices. This is based upon Will
Deacons
series [1]. This series attempts to fix the management of the EMU power domain
so that PMU can be
On Thu, May 10, 2012 at 3:05 AM, Jon Hunter jon-hun...@ti.com wrote:
From: Jon Hunter jon-hun...@ti.com
In order to use the CTI interrupts inconjunction with the DEBUGSS we need to
re-map the CTI IRQs to the DEBUGSS HWMOD. This is based upon Benoit Cousson's
patch [1].
[1]
On Thu, May 10, 2012 at 3:05 AM, Jon Hunter jon-hun...@ti.com wrote:
From: Ming Lei ming@canonical.com
The following modules is required to be enabled before configuring
cross trigger interface for enabling pmu irq:
l3_instr, l3_main_3, debugss
so build the arm-pmu device via
On Thu, May 10, 2012 at 3:05 AM, Jon Hunter jon-hun...@ti.com wrote:
From: Jon Hunter jon-hun...@ti.com
This patch is based upon Ming Lei's patch to add runtime PM support for OMAP4
[1]. In Ming's original patch the CTI interrupts were being enabled during
runtime when the PMU was used but
On Thu, May 10, 2012 at 5:06 PM, Roger Quadros rog...@ti.com wrote:
Hi,
On 05/03/2012 10:26 AM, R Sricharan wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4
On Wed, May 9, 2012 at 3:25 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, May 08, 2012 at 07:31:57PM +0530, Shilimkar, Santosh wrote:
Ok. Assuming you mean it's _not_ cleaner to have two domains where
manager overrides XN attributes Note that DRAM can be in the middle
On Tue, May 8, 2012 at 10:39 AM, Paul Walmsley p...@pwsan.com wrote:
On Wed, 2 May 2012, Santosh Shilimkar wrote:
Since OMAP4 code base now makes use of OMAP4 specific PRCM functions,
cm2xxx_3xxx.c need not be compiled for OMAP4 only builds.
Signed-off-by: Santosh Shilimkar
On Tue, May 8, 2012 at 10:45 AM, Paul Walmsley p...@pwsan.com wrote:
On Wed, 2 May 2012, Santosh Shilimkar wrote:
From: R Sricharan r.sricha...@ti.com
Instead of statically defining seperate arrays for every OMAP4+ archs,
have a generic init function to populate the arrays. This avoids the
On Tue, May 8, 2012 at 6:11 PM, Catalin Marinas catalin.mari...@arm.com wrote:
On Mon, May 07, 2012 at 02:42:29PM +0100, Santosh Shilimkar wrote:
From: R Sricharan r.sricha...@ti.com
ARM decompressor code setups entire 4GB address space pages.
Out of the 4GB, about 256MB are setup with normal
On Mon, May 7, 2012 at 4:02 PM, Cousson, Benoit b-cous...@ti.com wrote:
Hi Paul,
On 5/2/2012 11:09 AM, Paul Walmsley wrote:
On Fri, 27 Apr 2012, Hiremath, Vaibhav wrote:
I will be waiting for your comment and conformation on, which family
AM33xx
device should fall in? Please refer to the
On Fri, May 4, 2012 at 3:17 AM, Kevin Hilman khil...@ti.com wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
cpu_class_is_omap2() contains all OMAP2+ devices. So update the DMA code
cpu checks accordingly so that there is no need to patch
the file for any future OMAP2+ devices.
In
On Fri, May 4, 2012 at 12:59 PM, R Sricharan r.sricha...@ti.com wrote:
The system dma module has capabiities register indicating
the support for descriptor loading, constant fill, etc.
Use this instead of OMAP revision check to identify the features
supported runtime.
This avoids patching
On Wed, May 2, 2012 at 11:33 PM, Greg KH gre...@linuxfoundation.org wrote:
On Wed, May 02, 2012 at 12:20:24PM +0530, Santosh Shilimkar wrote:
Greg,
On Wednesday 02 May 2012 10:46 AM, Greg KH wrote:
On Fri, Apr 27, 2012 at 05:54:02PM +0530, Santosh Shilimkar wrote:
Add a driver for the EMIF
On Wed, May 2, 2012 at 3:26 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Wed, May 02, 2012 at 03:18:08PM +0530, Santosh Shilimkar wrote:
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
arch/arm/mach-omap2/Makefile | 160
On Wed, May 2, 2012 at 3:40 PM, Bedia, Vaibhav vaibhav.be...@ti.com wrote:
Hi Tero,
On Fri, Apr 20, 2012 at 15:03:34, Kristo, Tero wrote:
From: Rajendra Nayak rna...@ti.com
SAR/ROM code restores only CORE DPLL to its original state
post wakeup from OFF mode.
The rest of the DPLL's in OMAP4
On Wed, May 2, 2012 at 4:25 PM, Bedia, Vaibhav vaibhav.be...@ti.com wrote:
On Wed, May 02, 2012 at 15:48:01, Shilimkar, Santosh wrote:
On Wed, May 2, 2012 at 3:40 PM, Bedia, Vaibhav vaibhav.be...@ti.com wrote:
Hi Tero,
On Fri, Apr 20, 2012 at 15:03:34, Kristo, Tero wrote:
From: Rajendra
On Wed, May 2, 2012 at 5:10 PM, Bedia, Vaibhav vaibhav.be...@ti.com wrote:
On Wed, May 02, 2012 at 16:30:26, Shilimkar, Santosh wrote:
[...]
How ?
SRAM is sower memory than DDR so I don't see how it
will reduce latency.
I am just guessing if that's indeed the case ;)
Haven't done
On Wed, May 2, 2012 at 5:25 PM, Bedia, Vaibhav vaibhav.be...@ti.com wrote:
On Wed, May 02, 2012 at 17:17:08, Menon, Nishanth wrote:
On Wed, May 2, 2012 at 6:40 AM, Bedia, Vaibhav vaibhav.be...@ti.com wrote:
On Wed, May 02, 2012 at 16:30:26, Shilimkar, Santosh wrote:
[...]
How
On Tue, May 1, 2012 at 3:50 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
On 05/01/2012 11:55 AM, Shilimkar, Santosh wrote:
On May 1, 2012 1:46 PM, Daniel Lezcanodaniel.lezc...@linaro.org
wrote:
On 05/01/2012 12:58 AM, Kevin Hilman wrote:
Daniel Lezcanodaniel.lezc...@linaro.org
On Fri, Apr 27, 2012 at 2:09 AM, Kevin Hilman khil...@ti.com wrote:
NeilBrown ne...@suse.de writes:
[...]
From 644742ddae59731bc10aacde94645d7c49ca5ecd Mon Sep 17 00:00:00 2001
From: NeilBrown ne...@suse.de
Date: Wed, 25 Apr 2012 13:05:24 +1000
Subject: [PATCH] ARM: omap2+: set
+ Peter and Liam to comment
On Fri, Apr 27, 2012 at 7:28 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Can someone please hint on what audio is supported on these two OMAP
boards? From what I can tell, the answer is either nothing or hdmi,
both of which are useless to me if
On Wed, Apr 25, 2012 at 8:46 PM, Jon Hunter jon-hun...@ti.com wrote:
Hi Tero,
On 04/25/2012 02:26 AM, Tero Kristo wrote:
On Tue, 2012-04-24 at 13:22 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around
On Wed, Apr 25, 2012 at 10:04 AM, DebBarma, Tarun Kanti
tarun.ka...@ti.com wrote:
On Tue, Apr 24, 2012 at 9:34 PM, Tony Lindgren t...@atomide.com wrote:
* DebBarma, Tarun Kanti tarun.ka...@ti.com [120424 08:40]:
Hi Janusz,
On Tue, Apr 24, 2012 at 12:24 AM, DebBarma, Tarun Kanti
On Wed, Apr 25, 2012 at 12:56 PM, Tero Kristo t-kri...@ti.com wrote:
On Tue, 2012-04-24 at 13:22 -0500, Jon Hunter wrote:
Hi Tero,
On 04/20/2012 04:33 AM, Tero Kristo wrote:
From: Santosh Shilimkar santosh.shilim...@ti.com
Work around for Errata ID: i632 LPDDR2 Corruption After OFF Mode
On Tue, Apr 24, 2012 at 7:53 PM, Kevin Hilman khil...@ti.com wrote:
Iteration over all power domains in the idle path is unnecessary since
only power domains that are transitioning need to be accounted for.
Also PRCM register accesses are known to be expensive, so the
additional latency added
On Tue, Apr 24, 2012 at 7:53 PM, Kevin Hilman khil...@ti.com wrote:
Here's a first pass attempt to reduce the overhead of the pre/post
transitions by allowing them to be called per powerdomain and making
them conditional on powerdomain transtions.
This can be used for testing/measurements to
On Sat, Apr 21, 2012 at 2:29 AM, Paul Walmsley p...@pwsan.com wrote:
cc Santosh
Hi Kevin,
Nice changelog!
On Fri, 13 Apr 2012, Kevin Hilman wrote:
Without runtime PM enabled, hwmod needs to leave all IP blocks in an
enabled state by default so any driver access to the HW will succeed.
On Tue, Apr 24, 2012 at 3:15 PM, Vaibhav Hiremath hvaib...@ti.com wrote:
Current OMAP code supports couple of clocksource options based
on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer
and a gptimer which can run on 32KHz or system clock (e.g 38.4 MHz)
This patch series
On Tue, Apr 24, 2012 at 7:53 PM, Kevin Hilman khil...@ti.com wrote:
Iteration over all power domains in the idle path is unnecessary since
only power domains that are transitioning need to be accounted for.
Also PRCM register accesses are known to be expensive, so the
additional latency added
Afzal,
On Mon, Apr 23, 2012 at 4:26 PM, Mohammed, Afzal af...@ti.com wrote:
Hi Aneesh,
On Fri, Apr 13, 2012 at 01:28:55, V, Aneesh wrote:
Thanks. I will wait for your review then. Once I have your comments
I will re-work and submit in the new directory structure proposed.
Do you have a
On Mon, Apr 23, 2012 at 5:16 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Here's a patch which converts the SPI driver to use dma engine support.
It's more or less a mechanical replacement in this driver. Tested on
OMAP4430SDP ethernet (which basically means that udhcpc works.)
On Mon, Apr 23, 2012 at 7:57 PM, Tony Lindgren t...@atomide.com wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [120423 07:22]:
On Fri, Apr 20, 2012 at 03:22:33PM -0700, Tony Lindgren wrote:
* Russell King rmk+ker...@arm.linux.org.uk [120418 03:14]:
Using coherent DMA memory with
On Mon, Apr 23, 2012 at 7:57 PM, Greg KH g...@kroah.com wrote:
On Mon, Apr 23, 2012 at 04:34:46PM +0530, Shilimkar, Santosh wrote:
Afzal,
On Mon, Apr 23, 2012 at 4:26 PM, Mohammed, Afzal af...@ti.com wrote:
Hi Aneesh,
On Fri, Apr 13, 2012 at 01:28:55, V, Aneesh wrote:
Thanks. I
On Mon, Apr 9, 2012 at 12:24 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
On Tuesday 03 April 2012 08:36 PM, Santosh Shilimkar wrote:
On Tuesday 03 April 2012 10:34 AM, Kevin Hilman wrote:
Hi Santosh,
Santosh Shilimkar santosh.shilim...@ti.com writes:
The series adds the coupled
On Thu, Apr 12, 2012 at 6:40 PM, Greg KH g...@kroah.com wrote:
On Thu, Apr 12, 2012 at 12:17:49PM +0530, Santosh Shilimkar wrote:
I was hoping that we will have some thing like drivers/memory/*
but since it doesn't exist, we used drivers/misc.
Why not create it? I have no objection to that,
On Thu, Apr 12, 2012 at 6:57 PM, Lorenzo Pieralisi
lorenzo.pieral...@arm.com wrote:
Hi Santosh,
just posted a series whose aim is the same, please have a look and
let's try to merge the two approaches.
Sure ...
On Thu, Apr 12, 2012 at 12:29:47PM +0100, Santosh Shilimkar wrote:
The ARMv7
On Wed, Apr 11, 2012 at 6:30 AM, Ming Lei tom.leim...@gmail.com wrote:
On Tue, Apr 10, 2012 at 5:51 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Tue, Apr 10, 2012 at 2:59 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Apr 10, 2012 at 02:27:36PM +0530, Santosh
CC'ing LAKML
On Wed, Apr 11, 2012 at 2:04 PM, Tarun Kanti DebBarma
tarun.ka...@ti.com wrote:
Since hwmod framework now manages sysconfig context save/restore
there is no more need to touch this register in driver. Hence,
remove restore of sysconfig register in omap_timer_restore_context.
This
On Tue, Apr 10, 2012 at 2:59 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Apr 10, 2012 at 02:27:36PM +0530, Santosh Shilimkar wrote:
On Tuesday 10 April 2012 02:14 PM, Russell King - ARM Linux wrote:
On Mon, Apr 09, 2012 at 03:18:22PM -0500, Jon Hunter wrote:
True, but
On Tue, Apr 3, 2012 at 9:05 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Tue, Apr 03, 2012 at 00:05:38, Hilman, Kevin wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
[...]
I don't personally like to add features which hardly anybody use and
fundamentally broken with full
On Tue, Apr 3, 2012 at 2:55 PM, Will Deacon will.dea...@arm.com wrote:
Santosh,
On Wed, Jan 18, 2012 at 12:33:23PM +, Shilimkar, Santosh wrote:
On Wed, Jan 18, 2012 at 1:24 PM, Ming Lei ming@canonical.com wrote:
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c
b/arch/arm
On Tue, Apr 3, 2012 at 3:17 PM, Will Deacon will.dea...@arm.com wrote:
On Tue, Apr 03, 2012 at 10:42:30AM +0100, Shilimkar, Santosh wrote:
On Tue, Apr 3, 2012 at 2:55 PM, Will Deacon will.dea...@arm.com wrote:
Did you ever get to the bottom of this? This change really is required in
order
On Tue, Apr 3, 2012 at 6:04 PM, Will Deacon will.dea...@arm.com wrote:
On Tue, Apr 03, 2012 at 11:01:53AM +0100, Shilimkar, Santosh wrote:
On Tue, Apr 3, 2012 at 3:17 PM, Will Deacon will.dea...@arm.com wrote:
It seems that they're both needed to get reliable PMU operation. Without
On Tue, Apr 3, 2012 at 7:17 PM, Balaji T K balaj...@ti.com wrote:
platform_device pdev can be NULL if CONFIG_MMC_OMAP_HS is not set.
Add check for NULL pointer
Fixes the following boot crash seen with omap4sdp and omap4panda
when MMC is disabled.
Unable to handle kernel NULL pointer
On Mon, Apr 2, 2012 at 12:25 PM, Roger Quadros rog...@ti.com wrote:
Hi Santosh,
I came across the attached patch from you. I also came across this post
stating that it was decided not to send this patch upstream.
http://www.digipedia.pl/usenet/thread/18885/8437/#post8496
The problem is
On Mon, Apr 2, 2012 at 1:25 PM, Roger Quadros rog...@ti.com wrote:
On 04/02/2012 10:38 AM, Shilimkar, Santosh wrote:
On Mon, Apr 2, 2012 at 12:25 PM, Roger Quadros rog...@ti.com wrote:
Hi Santosh,
I came across the attached patch from you. I also came across this post
stating
On Mon, Apr 2, 2012 at 1:32 PM, Roger Quadros rog...@ti.com wrote:
On 04/02/2012 10:58 AM, Shilimkar, Santosh wrote:
On Mon, Apr 2, 2012 at 1:25 PM, Roger Quadros rog...@ti.com wrote:
On 04/02/2012 10:38 AM, Shilimkar, Santosh wrote:
On Mon, Apr 2, 2012 at 12:25 PM, Roger Quadros rog...@ti.com
On Tue, Apr 3, 2012 at 12:05 AM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
[...]
I don't personally like to add features which hardly anybody use and
fundamentally broken with full kernel.
Let's keep sane defaults, but not make it unreasonable
On Sat, Mar 31, 2012 at 7:00 AM, Ming Lei tom.leim...@gmail.com wrote:
On Fri, Mar 30, 2012 at 5:20 PM, Shilimkar, Santosh santosh.shilim...@ti.com
After Ming Lie's comment, the point that I came to my mind was,
certainly there will be resolution difference between these two
clocksources
On Sat, Mar 31, 2012 at 2:09 PM, Ming Lei tom.leim...@gmail.com wrote:
On Sat, Mar 31, 2012 at 2:30 PM, Shilimkar, Santosh
Since you need to recompile the kernel, you can very much tweak the
clocksource to use GPTIMER with sysl clock. Support for that is still
in place.
With current kernel
On Sun, Apr 1, 2012 at 7:09 AM, Ming Lei tom.leim...@gmail.com wrote:
On Sun, Apr 1, 2012 at 3:10 AM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Sat, Mar 31, 2012 at 2:09 PM, Ming Lei tom.leim...@gmail.com wrote:
On Sat, Mar 31, 2012 at 2:30 PM, Shilimkar, Santosh
Since you need
On Fri, Mar 30, 2012 at 12:04 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Wed, Mar 28, 2012 at 20:19:07, Shilimkar, Santosh wrote:
On Wed, Mar 28, 2012 at 8:07 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
On Wed, Mar 28, 2012
On Fri, Mar 30, 2012 at 1:37 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
Hi,
I just found out about OMAP4 errata i740:
DESCRIPTION
A bug has been identified in the interconnect agent handling the
connect-disconnect protocol between an
initiator and interconnect. When the disconnect
On Fri, Mar 30, 2012 at 2:05 PM, R Sricharan r.sricha...@ti.com wrote:
With CONFIG_OMAP4_ERRATA_I688 enabled, omap2+ build
was broken as below.
arch/arm/kernel/io.c: In function '_memcpy_toio':
arch/arm/kernel/io.c:29: error: implicit declaration of function
'outer_sync'
On Fri, Mar 30, 2012 at 2:42 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Fri, Mar 30, 2012 at 14:08:20, Shilimkar, Santosh wrote:
On Friday 30 March 2012 02:02 PM, Hiremath, Vaibhav wrote:
On Fri, Mar 30, 2012 at 13:11:35, Shilimkar, Santosh wrote:
[]
With this patch, will you
On Fri, Mar 30, 2012 at 2:58 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Fri, Mar 30, 2012 at 14:50:02, Shilimkar, Santosh wrote:
On Fri, Mar 30, 2012 at 2:42 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Fri, Mar 30, 2012 at 14:08:20, Shilimkar, Santosh wrote:
On Friday 30 March 2012
:
On Friday 30 March 2012 02:01 PM, Santosh Shilimkar wrote:
+ Kevin
On Friday 30 March 2012 01:56 PM, Tomi Valkeinen wrote:
On Fri, 2012-03-30 at 13:51 +0530, Shilimkar, Santosh wrote:
On Fri, Mar 30, 2012 at 1:37 PM, Tomi
Valkeinentomi.valkei...@ti.com wrote:
[...]
I had a general
On Fri, Mar 30, 2012 at 4:47 PM, Archit Taneja a0393...@ti.com wrote:
On Friday 30 March 2012 04:34 PM, Shilimkar, Santosh wrote:
On Fri, Mar 30, 2012 at 4:26 PM, Archit Tanejaa0393...@ti.com wrote:
On Friday 30 March 2012 03:59 PM, Santosh Shilimkar wrote:
On Friday 30 March 2012 03:53
On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
On Monday 19 March 2012
On Wed, Mar 28, 2012 at 8:07 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Wed, Mar 28, 2012 at 19:50:02, Shilimkar, Santosh wrote:
On Wed, Mar 28, 2012 at 7:46 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Wed, Mar 21, 2012 at 19:30:01, Shilimkar, Santosh wrote:
On Wed, Mar 21, 2012
On Fri, Mar 23, 2012 at 12:06 PM, Afzal Mohammed af...@ti.com wrote:
Hi,
Convert GPCM code to be a driver. Existing GPMC
NAND platform handling has been modified to work
with the new GPMC driver (patches 2 3). Patch 5
is to test the driver in OMAP3EVM.
Once all the users has been
On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
This patchset is a proposition to improve a bit the code.
The changes are code cleanup and does not change the behavior of the
driver itself.
Thanks. Will have a look at your series.
A couple a things call my
On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
The 'valid' field is never used in the code, let's remove it.
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
It is used during the registration. This field has been very useful for
debug when need to
On Wed, Mar 21, 2012 at 4:13 PM, Daniel Lezcano
daniel.lezc...@linaro.org wrote:
On 03/21/2012 10:56 AM, Santosh Shilimkar wrote:
On Wednesday 21 March 2012 03:21 PM, Daniel Lezcano wrote:
On 03/21/2012 10:36 AM, Shilimkar, Santosh wrote:
On Wed, Mar 21, 2012 at 2:57 PM, Daniel Lezcano
On Wed, Mar 21, 2012 at 5:12 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Mon, Mar 19, 2012 at 17:45:32, Shilimkar, Santosh wrote:
On Monday 19 March 2012 05:14 PM, Ming Lei wrote:
On Mon, Mar 19, 2012 at 7:11 PM, Hiremath, Vaibhav hvaib...@ti.com wrote:
I think you made very good point
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