On Thu, 28 Mar 2013, Rajendra Nayak wrote:
> omap3_noncore_dpll_set_rate() attempts an enable of bypass clk as well
> as ref clk for every .set_rate attempt on a noncore DPLL, regardless of
> whether the .set_rate results in the DPLL being locked or put in bypass.
> Early at boot, while some of th
On Thursday 28 March 2013 10:02 PM, Mike Turquette wrote:
> Quoting Rajendra Nayak (2013-03-28 03:59:41)
>> omap3_noncore_dpll_set_rate() attempts an enable of bypass clk as well
>> as ref clk for every .set_rate attempt on a noncore DPLL, regardless of
>> whether the .set_rate results in the DPLL
Quoting Rajendra Nayak (2013-03-28 03:59:41)
> omap3_noncore_dpll_set_rate() attempts an enable of bypass clk as well
> as ref clk for every .set_rate attempt on a noncore DPLL, regardless of
> whether the .set_rate results in the DPLL being locked or put in bypass.
> Early at boot, while some of t
omap3_noncore_dpll_set_rate() attempts an enable of bypass clk as well
as ref clk for every .set_rate attempt on a noncore DPLL, regardless of
whether the .set_rate results in the DPLL being locked or put in bypass.
Early at boot, while some of these DPLLs are programmed and locked
(using .set_rate
