On Fri, Mar 19, 2010 at 08:58:05AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [100319 01:49]:
On Thu, Mar 18, 2010 at 06:35:21PM -0700, Tony Lindgren wrote:
-#if defined(CONFIG_HAS_TLS_REG)
- mcr p15, 0, r3, c13, c0, 3 @ set TLS register
* Russell King - ARM Linux li...@arm.linux.org.uk [100322 17:12]:
On Fri, Mar 19, 2010 at 08:58:05AM -0700, Tony Lindgren wrote:
* Russell King - ARM Linux li...@arm.linux.org.uk [100319 01:49]:
On Thu, Mar 18, 2010 at 06:35:21PM -0700, Tony Lindgren wrote:
-#if
On Thu, Mar 18, 2010 at 06:35:21PM -0700, Tony Lindgren wrote:
-#if defined(CONFIG_HAS_TLS_REG)
- mcr p15, 0, r3, c13, c0, 3 @ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
- mov r4, #0x0fff
- str r3, [r4, #-15] @ TLS val at
On Fri, Mar 19, 2010 at 03:46:45AM +, Jamie Lokier wrote:
I'm thinking, why not an alternative() macro like on x86, which is a
very nice way to describe run-time patches of one or a few instructions
which depend on arch feature bits.
Having XIP support prevents that kind of thing.
--
To
* Russell King - ARM Linux li...@arm.linux.org.uk [100319 01:49]:
On Thu, Mar 18, 2010 at 06:35:21PM -0700, Tony Lindgren wrote:
-#if defined(CONFIG_HAS_TLS_REG)
- mcr p15, 0, r3, c13, c0, 3 @ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
- mov r4, #0x0fff
* Tony Lindgren t...@atomide.com [100318 09:55]:
* Catalin Marinas catalin.mari...@arm.com [100318 04:10]:
On Wed, 2010-03-17 at 19:11 +, Tony Lindgren wrote:
* Catalin Marinas catalin.mari...@arm.com [100317 11:04]:
On Wed, 2010-03-17 at 17:57 +, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [100318 18:31]:
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -269,6 +269,24 @@ static void __init cacheid_init(void)
extern struct proc_info_list *lookup_processor_type(unsigned int);
extern struct machine_desc *lookup_machine_type(unsigned
Tony Lindgren wrote:
Also, I wonder if the change __kuser_get_tls is safe?
+ ldr r0, [pc, #(16 - 8)] @ TLS set at 0x0ff0?
+ cmp r0, #0 @ assume hw TLS if not set
+ mrceq p15, 0, r0, c13, c0, 3 @ read TLS register
You
