On 04/30/2014 02:39 PM, Peter Ujfalusi wrote:
In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Thanks, queued for 3.15-rc/ti-clk-drv.
-Tero
---
In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
drivers/clk/ti/clk-54xx.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/ti/clk-54xx.c
