* Tero Kristo [150225 00:05]:
> On 02/24/2015 06:27 PM, Tony Lindgren wrote:
> >* Ravikumar Kattekola [150219 08:13]:
> >>On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
> >>>Fix bypass clock source for a few DPLLs.
> >>>
> >>>On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are conn
On 02/24/2015 06:27 PM, Tony Lindgren wrote:
* Ravikumar Kattekola [150219 08:13]:
On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
Fix bypass clock source for a few DPLLs.
On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
to a mux and the output from mux is routed to
* Ravikumar Kattekola [150219 08:13]:
> On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
> >Fix bypass clock source for a few DPLLs.
> >
> >On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
> >to a mux and the output from mux is routed to the bypass clkout.
> >Add a mux-cl
On 1/31/2015 10:36 PM, Ravikumar Kattekola wrote:
Fix bypass clock source for a few DPLLs.
On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
to a mux and the output from mux is routed to the bypass clkout.
Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as pare
Fix bypass clock source for a few DPLLs.
On DRA7x/OMAP5, for a few DPLLs, both CLKINP and CLKINPULOW are connected
to a mux and the output from mux is routed to the bypass clkout.
Add a mux-clock as bypass clock with CLKINP and CLKINPULOW as parents.
Tested against:
tree: https://git.ker
