On Sat, Feb 19, 2011 at 5:03 AM, David Cohen daco...@gmail.com wrote:
Hi,
On Fri, Feb 18, 2011 at 7:08 PM, Lesly A M lesl...@ti.com wrote:
Workaround for TWL5030 Silicon Errata 27 28:
27 - VDD1, VDD2, may have glitches when their output value is updated.
28 - VDD1 and / or
Hi David,
On Sun, Feb 20, 2011 at 3:32 AM, David Cohen daco...@gmail.com wrote:
On Sat, Feb 19, 2011 at 2:44 AM, David Cohen daco...@gmail.com wrote:
On Sat, Feb 19, 2011 at 1:33 AM, David Cohen daco...@gmail.com wrote:
Hi,
On Fri, Feb 18, 2011 at 7:08 PM, Lesly A M lesl...@ti.com wrote:
On Sat, Feb 19, 2011 at 2:44 AM, David Cohen daco...@gmail.com wrote:
On Sat, Feb 19, 2011 at 1:33 AM, David Cohen daco...@gmail.com wrote:
Hi,
On Fri, Feb 18, 2011 at 7:08 PM, Lesly A M lesl...@ti.com wrote:
Workaround for TWL5030 Silicon Errata 27 28:
27 - VDD1, VDD2, may have
Workaround for TWL5030 Silicon Errata 27 28:
27 - VDD1, VDD2, may have glitches when their output value is updated.
28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock
is switched from internal to external.
Errata 27:
If the DCDC
Hi,
On Fri, Feb 18, 2011 at 7:08 PM, Lesly A M lesl...@ti.com wrote:
Workaround for TWL5030 Silicon Errata 27 28:
27 - VDD1, VDD2, may have glitches when their output value is updated.
28 - VDD1 and / or VDD2 DCDC clock may stop working when internal clock
is
On Sat, Feb 19, 2011 at 1:33 AM, David Cohen daco...@gmail.com wrote:
Hi,
On Fri, Feb 18, 2011 at 7:08 PM, Lesly A M lesl...@ti.com wrote:
Workaround for TWL5030 Silicon Errata 27 28:
27 - VDD1, VDD2, may have glitches when their output value is updated.
28 - VDD1 and / or