On Sunday 14 July 2013 05:37 PM, Kevin Hilman wrote:
On 07/09/2013 08:27 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
DRA7xx has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs,
On 07/09/2013 08:27 AM, Rajendra Nayak wrote:
From: R Sricharan r.sricha...@ti.com
DRA7xx has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs, ARCH_NR_GPIO is set
to 512 instead of present 256.
From: R Sricharan r.sricha...@ti.com
DRA7xx has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs, ARCH_NR_GPIO is set
to 512 instead of present 256.
Signed-off-by: R Sricharan r.sricha...@ti.com
