Paul Walmsley writes:
> On Thu, 26 Nov 2009, Thara Gopinath wrote:
>
>> MPU power domain bank 0 bits are displayed in position of bank 1
>> in PWRSTS and PREPWRSTS registers. So read them from correct
>> position
>>
>> Signed-off-by: Thara Gopinath
>> Cc: Kevin Hilman
Signed-off-by: Kevin Hil
On Thu, 26 Nov 2009, Thara Gopinath wrote:
> MPU power domain bank 0 bits are displayed in position of bank 1
> in PWRSTS and PREPWRSTS registers. So read them from correct
> position
>
> Signed-off-by: Thara Gopinath
> Cc: Kevin Hilman
Thanks Thara, will queue this up.
- Paul
--
To unsubscri
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath
Cc: Kevin Hilman
---
arch/arm/mach-omap2/powerdomain.c |6 ++
arch/arm/mach-omap2/powerdomains34xx.h|
usly NAK'ed strcmp()s for this sort of
> >>thing, for good reason, and testing the PRCM internal module offset has
> >>many of the same problems.
> >>
> >>Sound reasonable?
> >>
> >>
> >>- Paul
> >>
> >>
> >&
PM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; khil...@deeprootsystems.com
>>Subject: RE: [PATCH V2] OMAP3: PM: Fix for MPU power domain MEM BANK position
>>
>>Hi Thara,
>>
>>On Thu, 15 Oct 2009, Gopinath, Thara wrote:
>>
>>> Thanks
Thara
> >>Cc: linux-omap@vger.kernel.org; khil...@deeprootsystems.com
> >>Subject: Re: [PATCH V2] OMAP3: PM: Fix for MPU power domain MEM BANK
> >>position
> >>
> >>Hi Thara,
> >>
> >>I regret the delay. A comment:
> >>
>
>>-Original Message-
>>From: Paul Walmsley [mailto:p...@pwsan.com]
>>Sent: Thursday, October 15, 2009 4:51 AM
>>To: Gopinath, Thara
>>Cc: linux-omap@vger.kernel.org; khil...@deeprootsystems.com
>>Subject: Re: [PATCH V2] OMAP3: PM: Fix for MPU power domain MEM
Hi Thara,
I regret the delay. A comment:
On Fri, 28 Aug 2009, Thara Gopinath wrote:
> MPU power domain bank 0 bits are displayed in position of bank 1
> in PWRSTS and PREPWRSTS registers. So read them from correct
> position
Indeed. What do you think about a slightly different approach: chang
Thara Gopinath writes:
> MPU power domain bank 0 bits are displayed in position of bank 1
> in PWRSTS and PREPWRSTS registers. So read them from correct
> position
>
> Signed-off-by: Thara Gopinath
> ---
> Patch refresh issue.
>
> arch/arm/mach-omap2/powerdomain.c | 19 +++
>
MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position
Signed-off-by: Thara Gopinath
---
Patch refresh issue.
arch/arm/mach-omap2/powerdomain.c | 19 +++
1 files changed, 19 insertions(+), 0 deleti
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