Kevin,
-Original Message-
From: Kevin Hilman [mailto:khil...@deeprootsystems.com]
Sent: Tuesday, May 18, 2010 10:07 PM
To: Sripathy, Vishwanath
Cc: Gulati, Shweta; linux-omap@vger.kernel.org
Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Sripathy, Vishwanath
Hi Vishwa,
On 5/13/2010 12:12 PM, shweta gulati wrote:
From: Vishwanath Sripathyvishwanath...@ti.com
OMAP3430/3630 has a Silicon bug because of which SDRC is
released from IDLE even before Core DPLL has locked. This leads
to undefined behaviour of SDRC DLL.
This patch has workaround for the
Hi Benoit,
-Original Message-
From: Cousson, Benoit
Sent: Wednesday, May 19, 2010 5:28 PM
To: Gulati, Shweta
Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath
Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Hi Vishwa,
On 5/13/2010 12:12 PM, shweta gulati
On 5/19/2010 3:50 PM, Sripathy, Vishwanath wrote:
Hi Benoit,
-Original Message-
From: Cousson, Benoit
Sent: Wednesday, May 19, 2010 5:28 PM
To: Gulati, Shweta
Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath
Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
Hi
Hi Benoit,
-Original Message-
From: Cousson, Benoit
Sent: Wednesday, May 19, 2010 8:00 PM
To: Sripathy, Vishwanath
Cc: Gulati, Shweta; linux-omap@vger.kernel.org
Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
On 5/19/2010 3:50 PM, Sripathy, Vishwanath wrote
On 5/19/2010 4:37 PM, Sripathy, Vishwanath wrote:
Hi Benoit,
-Original Message-
From: Cousson, Benoit
Sent: Wednesday, May 19, 2010 8:00 PM
To: Sripathy, Vishwanath
Cc: Gulati, Shweta; linux-omap@vger.kernel.org
Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
On 5
Kevin,
-Original Message-
From: Kevin Hilman [mailto:khil...@deeprootsystems.com]
Sent: Friday, May 14, 2010 11:28 PM
To: Gulati, Shweta
Cc: linux-omap@vger.kernel.org; Sripathy, Vishwanath
Subject: Re: [PATCH V2] OMAP3: PM: Workaround for DPLL3 Lock issue
shweta gulati
Sripathy, Vishwanath vishwanath...@ti.com writes:
All that being said, why is the voltage level being programmed here?
It seems to me that all of this errata handling should be
self-contained in the voltage layer.
I am not sure if entire errata can be contained in voltage
layer. This is
shweta gulati shweta.gul...@ti.com writes:
From: Vishwanath Sripathy vishwanath...@ti.com
OMAP3430/3630 has a Silicon bug because of which SDRC is
released from IDLE even before Core DPLL has locked. This leads
to undefined behaviour of SDRC DLL.
This patch has workaround for the same.
From: Vishwanath Sripathy vishwanath...@ti.com
OMAP3430/3630 has a Silicon bug because of which SDRC is
released from IDLE even before Core DPLL has locked. This leads
to undefined behaviour of SDRC DLL.
This patch has workaround for the same.
Description of WA for 3430:
Initialization:
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