On 08/01/2012 03:47 PM, Will Deacon wrote:
> On Wed, Aug 01, 2012 at 12:07:16AM +0100, Jon Hunter wrote:
>> I have just updated my pmu branch for omap3/4. You can pull my latest
>> patches from [1].
>
> Great, thanks for that. I've pushed out to perf/omap4 and I've also
> included your runtime PM
On Wed, Aug 01, 2012 at 12:07:16AM +0100, Jon Hunter wrote:
> I have just updated my pmu branch for omap3/4. You can pull my latest
> patches from [1].
Great, thanks for that. I've pushed out to perf/omap4 and I've also
included your runtime PM hooks in my perf/updates branch. I have a fair
amount
Hi Will,
On 07/31/2012 10:14 AM, Will Deacon wrote:
> On Thu, Jul 26, 2012 at 04:16:15PM +0100, Jon Hunter wrote:
>> On 07/26/2012 10:05 AM, Will Deacon wrote:
>>> Ok, thanks for updating me. I've pushed the patches out onto my
>>> perf/omap4-dev branch as that seems to be a good place to collate
On Thu, Jul 26, 2012 at 04:16:15PM +0100, Jon Hunter wrote:
> On 07/26/2012 10:05 AM, Will Deacon wrote:
> > Ok, thanks for updating me. I've pushed the patches out onto my
> > perf/omap4-dev branch as that seems to be a good place to collate the
> > current state of things. I've not tried doing an
On 07/26/2012 10:05 AM, Will Deacon wrote:
> On Thu, Jul 26, 2012 at 01:41:23AM +0100, Jon Hunter wrote:
>> Hi Will,
>
> Hi Jon,
>
>> On 07/05/2012 07:40 PM, Jon Hunter wrote:
>> I just wanted to let you know that I have been updating the PMU patches
>> for OMAP. Latest can be found here [1]. I
On Thu, Jul 26, 2012 at 01:41:23AM +0100, Jon Hunter wrote:
> Hi Will,
Hi Jon,
> On 07/05/2012 07:40 PM, Jon Hunter wrote:
> I just wanted to let you know that I have been updating the PMU patches
> for OMAP. Latest can be found here [1]. I have not included Paul's patch
> [2] in this series at t
Hi Will,
On 07/05/2012 07:40 PM, Jon Hunter wrote:
> Hi Will,
>
> On 07/02/2012 05:01 PM, Will Deacon wrote:
>> On Mon, Jul 02, 2012 at 05:50:38PM +0100, Jon Hunter wrote:
>>> On 07/02/2012 04:55 AM, Will Deacon wrote:
Did you have any luck getting to the bottom of this?
>>>
>>> I am st
Hi Will,
On 07/02/2012 05:01 PM, Will Deacon wrote:
> On Mon, Jul 02, 2012 at 05:50:38PM +0100, Jon Hunter wrote:
>> On 07/02/2012 04:55 AM, Will Deacon wrote:
>>>
>>> Did you have any luck getting to the bottom of this?
>>
>> I am still waiting for feedback from design. They were trying to confir
On Mon, Jul 02, 2012 at 05:50:38PM +0100, Jon Hunter wrote:
> On 07/02/2012 04:55 AM, Will Deacon wrote:
> >
> > Did you have any luck getting to the bottom of this?
>
> I am still waiting for feedback from design. They were trying to confirm
> my observations. Unfortunately, it is taking some ti
Hi Will,
On 07/02/2012 04:55 AM, Will Deacon wrote:
> Hi Jon,
>
> Did you have any luck getting to the bottom of this?
I am still waiting for feedback from design. They were trying to confirm
my observations. Unfortunately, it is taking some time. I will ping them
again.
> It would be good to t
Hi Jon,
Did you have any luck getting to the bottom of this?
It would be good to take your PMU suspend/resume patches once we know that
they will get used.
On Tue, Jun 12, 2012 at 11:41:27PM +0100, Jon Hunter wrote:
> On 06/12/2012 04:31 PM, Will Deacon wrote:
> > That's understandable -- one of
On 06/12/2012 04:31 PM, Will Deacon wrote:
> On Tue, Jun 12, 2012 at 10:17:16PM +0100, Jon Hunter wrote:
>> Hi Will,
>
> Hi Jon,
>
>> On 06/12/2012 04:28 AM, Will Deacon wrote:
>>>
>>> Well, I tried that and the results are pretty whacky: the event counters do
>>> indeed tick but interrupts only
On Tue, Jun 12, 2012 at 10:17:16PM +0100, Jon Hunter wrote:
> Hi Will,
Hi Jon,
> On 06/12/2012 04:28 AM, Will Deacon wrote:
> >
> > Well, I tried that and the results are pretty whacky: the event counters do
> > indeed tick but interrupts only fire if I pin the perf task to CPU1! What's
> > more
Hi Will,
On 06/12/2012 04:28 AM, Will Deacon wrote:
> On Mon, Jun 11, 2012 at 08:01:23PM +0100, Jon Hunter wrote:
>> Hi Will,
>
> Hello,
>
>> On 06/11/2012 12:39 PM, Will Deacon wrote:
>>> This looks better to me, so I took it for a spin on my 4460 (thanks
>>> Nicolas!)
>>> and noticed that onl
On Mon, Jun 11, 2012 at 08:01:23PM +0100, Jon Hunter wrote:
> Hi Will,
Hello,
> On 06/11/2012 12:39 PM, Will Deacon wrote:
> > This looks better to me, so I took it for a spin on my 4460 (thanks
> > Nicolas!)
> > and noticed that only the cycle counter seems to tick -- the event counters
> > alw
Hi Will,
On 06/11/2012 12:39 PM, Will Deacon wrote:
> On Fri, Jun 08, 2012 at 04:24:32PM +0100, Jon Hunter wrote:
>> Hi Will,
>
> Hi Jon,
>
>> Here is an updated version. I was going to send out a V3, but I wanted
>> to wait to see if others had more comments first.
>
> This looks better to me,
On Fri, Jun 08, 2012 at 04:24:32PM +0100, Jon Hunter wrote:
> Hi Will,
Hi Jon,
> Here is an updated version. I was going to send out a V3, but I wanted
> to wait to see if others had more comments first.
This looks better to me, so I took it for a spin on my 4460 (thanks Nicolas!)
and noticed th
Hi Will,
On 06/08/2012 04:47 AM, Will Deacon wrote:
> Hi Jon,
>
> On Thu, Jun 07, 2012 at 10:22:03PM +0100, Jon Hunter wrote:
>> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
>> index 186c8cb..00adb98 100644
>> --- a/arch/arm/kernel/perf_event.c
>> +++ b/arch/arm/kernel
Hi Will,
On 06/08/2012 04:47 AM, Will Deacon wrote:
> Hi Jon,
>
> On Thu, Jun 07, 2012 at 10:22:03PM +0100, Jon Hunter wrote:
>> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
>> index 186c8cb..00adb98 100644
>> --- a/arch/arm/kernel/perf_event.c
>> +++ b/arch/arm/kernel
Hi Jon,
On Thu, Jun 07, 2012 at 10:22:03PM +0100, Jon Hunter wrote:
> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> index 186c8cb..00adb98 100644
> --- a/arch/arm/kernel/perf_event.c
> +++ b/arch/arm/kernel/perf_event.c
> @@ -20,6 +20,7 @@
> #include
> #include
>
Add runtime PM support to the ARM PMU driver so that devices such as OMAP
supporting dynamic PM can use the platform->runtime_* hooks to initialise
hardware at runtime. Without having these runtime PM hooks in place any
configuration of the PMU hardware would be lost when low power states are
enter
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