Rajendra Nayak <rna...@ti.com> writes:
> Do not skip the sysc programming in the hmwod framework based
> on the cached value alone, since at times the module might have lost
> context (due to the Powerdomain in which the module belongs
> transitions to either Open Switch RET or OFF).
>
> Identifying if a module has lost context requires atleast one
> register read, and since a register read has more latency than
> a write, it makes sense to do a blind write always.
>
> Signed-off-by: Rajendra Nayak <rna...@ti.com>
> Cc: Paul Walmsley <p...@pwsan.com>
> Cc: Benoit Cousson <b-cous...@ti.com>
> Cc: Santosh Shilimkar <santosh.shilim...@ti.com>
> Cc: Kevin Hilman <khil...@deeprootsystems.com>
Acked-by: Kevin Hilman <khil...@deeprootsystems.com>
> ---
> arch/arm/mach-omap2/omap_hwmod.c | 7 +++----
> 1 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod.c
> b/arch/arm/mach-omap2/omap_hwmod.c
> index 5a30658..aadd6dc 100644
> --- a/arch/arm/mach-omap2/omap_hwmod.c
> +++ b/arch/arm/mach-omap2/omap_hwmod.c
> @@ -209,10 +209,9 @@ static void _write_sysconfig(u32 v, struct omap_hwmod
> *oh)
>
> /* XXX ensure module interface clock is up */
>
> - if (oh->_sysc_cache != v) {
> - oh->_sysc_cache = v;
> - omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
> - }
> + /* Module might have lost context, always update cache and register */
> + oh->_sysc_cache = v;
> + omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
> }
>
> /**
--
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