On Tuesday 15 October 2013 12:57 PM, Benoit Cousson wrote:
> Hi Rajendra,
>
> On 09/10/2013 18:45, Benoit Cousson wrote:
>> + A couple of DT maintainers
>>
>> On 09/10/2013 18:41, Rajendra Nayak wrote:
>>> On Wednesday 09 October 2013 08:43 PM, Benoit Cousson wrote:
Hi Rajendra,
On
Hi Rajendra,
On 09/10/2013 18:45, Benoit Cousson wrote:
+ A couple of DT maintainers
On 09/10/2013 18:41, Rajendra Nayak wrote:
On Wednesday 09 October 2013 08:43 PM, Benoit Cousson wrote:
Hi Rajendra,
On 09/10/2013 12:11, Rajendra Nayak wrote:
On OMAP we have co-processor IPs, memory contr
On Wednesday 09 October 2013 08:43 PM, Benoit Cousson wrote:
> Hi Rajendra,
>
> On 09/10/2013 12:11, Rajendra Nayak wrote:
>> On OMAP we have co-processor IPs, memory controllers,
>> GPIOs which control regulators and power switches to
>> PMIC, and SoC internal Bus IPs, some or most of which
>> sh
+ A couple of DT maintainers
On 09/10/2013 18:41, Rajendra Nayak wrote:
On Wednesday 09 October 2013 08:43 PM, Benoit Cousson wrote:
Hi Rajendra,
On 09/10/2013 12:11, Rajendra Nayak wrote:
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches
Hi Rajendra,
On 09/10/2013 12:11, Rajendra Nayak wrote:
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are e
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to
