On 06/17/2013 12:16 PM, Mark Brown wrote:
On Fri, Jun 14, 2013 at 07:12:08PM +0300, Illia Smyrnov wrote:
The MCSPI controller has a built-in FIFO buffer to unload the DMA or interrupt
handler and improve data throughput. This patch adds FIFO buffer support for SPI
transfers in DMA mode.
This
On Fri, Jun 14, 2013 at 07:12:08PM +0300, Illia Smyrnov wrote:
> The MCSPI controller has a built-in FIFO buffer to unload the DMA or interrupt
> handler and improve data throughput. This patch adds FIFO buffer support for
> SPI
> transfers in DMA mode.
This looks good but doesn't apply against m
The MCSPI controller has a built-in FIFO buffer to unload the DMA or interrupt
handler and improve data throughput. This patch adds FIFO buffer support for SPI
transfers in DMA mode.
For SPI transfers in DMA mode, the largest possible FIFO buffer size will be
calculated and set up. The FIFO won't
