Re: [RFC][PATCH] [I2C]pass scll, sclh through board file for Errata i585

2010-04-28 Thread Nishanth Menon
Krishnamoorthy, Balaji T had written, on 04/28/2010 07:34 AM, the following: From: Tony Lindgren [mailto:t...@atomide.com] * balaj...@ti.com [100419 07:59]: From: Balaji T K Errata ID: i535 - I2C1 to 3 SCL low period is shorter in FS mode Due to IO cell influence, I2C1 to 3 SCL low period can

RE: [RFC][PATCH] [I2C]pass scll, sclh through board file for Errata i585

2010-04-28 Thread Krishnamoorthy, Balaji T
> From: Tony Lindgren [mailto:t...@atomide.com] > * balaj...@ti.com [100419 07:59]: > > From: Balaji T K > > > > Errata ID: i535 - I2C1 to 3 SCL low period is shorter in FS mode > > Due to IO cell influence, I2C1 to 3 SCL low period can be shorter than > expected. > > As a result, I2C AC timing (

Re: [RFC][PATCH] [I2C]pass scll, sclh through board file for Errata i585

2010-04-26 Thread Tony Lindgren
* balaj...@ti.com [100419 07:59]: > From: Balaji T K > > Errata ID: i535 - I2C1 to 3 SCL low period is shorter in FS mode > Due to IO cell influence, I2C1 to 3 SCL low period can be shorter than > expected. > As a result, I2C AC timing (SCL minimum low period) in FS mode may not meet > the ti

[RFC][PATCH] [I2C]pass scll, sclh through board file for Errata i585

2010-04-19 Thread balajitk
From: Balaji T K Errata ID: i535 - I2C1 to 3 SCL low period is shorter in FS mode Due to IO cell influence, I2C1 to 3 SCL low period can be shorter than expected. As a result, I2C AC timing (SCL minimum low period) in FS mode may not meet the timing configured by software. I2C1 to 3, SCL low