From: Rajendra Nayak rna...@ti.com
The OMAP4460 platform needs DCC (Duty cycle correction)
enabled for frequencies above 1GHz from the MPU DPLL.
Further, on OMAP4460 when the MPU Frequency is above 748Mhz,
the programmable divider for the Async bridge to ABE must be
set to MPU-Freq/8. For lower
On Wed, May 25, 2011 at 06:56:56PM -0700, Nishanth Menon wrote:
...
@@ -427,6 +465,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned
long rate)
u16 freqsel = 0;
struct dpll_data *dd;
int ret;
+ unsigned long orig_rate = 0;
if (!clk || !rate)
On 5/26/2011 8:46 AM, Todd Poynor wrote:
On Wed, May 25, 2011 at 06:56:56PM -0700, Nishanth Menon wrote:
...
@@ -427,6 +465,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned
long rate)
u16 freqsel = 0;
struct dpll_data *dd;
int ret;
+ unsigned long
On Wed, May 25, 2011 at 21:13, Rajendra Nayak rna...@ti.com wrote:
On 5/26/2011 8:46 AM, Todd Poynor wrote:
On Wed, May 25, 2011 at 06:56:56PM -0700, Nishanth Menon wrote:
...
@@ -427,6 +465,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk,
unsigned long rate)
u16 freqsel = 0;
