Re: [PATCH V2 4/4] ARM: OMAP3+: PM: VP: ensure VP is idle before disable

2012-06-04 Thread Kevin Hilman
Menon, Nishanth n...@ti.com writes: Regards, Nishanth Menon On Fri, Jun 1, 2012 at 4:03 PM, Kevin Hilman khil...@ti.com wrote: Nishanth Menon n...@ti.com writes: From: Wenbiao Wang ww...@ti.com Voltage Processor state machine transition to disable need to occur from IDLE state. When we

Re: [PATCH V2 4/4] ARM: OMAP3+: PM: VP: ensure VP is idle before disable

2012-06-01 Thread Kevin Hilman
Nishanth Menon n...@ti.com writes: From: Wenbiao Wang ww...@ti.com Voltage Processor state machine transition to disable need to occur from IDLE state. When we transition OPP in a functioning system, the call sequence for an OPP transition is as follows: omap_sr_disable - sr class 3

Re: [PATCH V2 4/4] ARM: OMAP3+: PM: VP: ensure VP is idle before disable

2012-06-01 Thread Menon, Nishanth
Regards, Nishanth Menon On Fri, Jun 1, 2012 at 4:03 PM, Kevin Hilman khil...@ti.com wrote: Nishanth Menon n...@ti.com writes: From: Wenbiao Wang ww...@ti.com Voltage Processor state machine transition to disable need to occur from IDLE state. When we transition OPP in a functioning

[PATCH V2 4/4] ARM: OMAP3+: PM: VP: ensure VP is idle before disable

2012-05-31 Thread Nishanth Menon
From: Wenbiao Wang ww...@ti.com Voltage Processor state machine transition to disable need to occur from IDLE state. When we transition OPP in a functioning system, the call sequence for an OPP transition is as follows: omap_sr_disable - sr class 3 disable - vp disable