Hi Geert,
Thanks for your comment.
On 11/07/2016 07:25 PM, Geert Uytterhoeven wrote:
Hi Hiep,
On Mon, Nov 7, 2016 at 2:00 AM, Cao Minh Hiep wrote:
From: Hiep Cao Minh
This patch rewrites the name of rspi_pio_transfer_in_or_out
function.
Signed-off-by: Hiep Cao Minh
Acked-by: Geert Uytte
From: Kuninori Morimoto
Current dw-hdmi is supporting sound via AHB bus, but it has
I2S audio feature too. This patch adds I2S audio support to dw-hdmi.
This HDMI I2S is supported by using ALSA SoC common HDMI encoder
driver.
Tested-by: Jose Abreu
Signed-off-by: Kuninori Morimoto
---
v3 -> v4
From: Hiep Cao Minh
This patch rewrites the name of rspi_pio_transfer_in_or_out
function.
Signed-off-by: Hiep Cao Minh
Acked-by: Geert Uytterhoeven
---
drivers/spi/spi-rspi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rs
Hi Russell
> > > This is wrong. If platform is NULL, PTR_ERR() will return zero, which
> > > will be interpreted as success. Please, avoid using IS_ERR_OR_NULL(),
> > > it leads to exactly this kind of cockup - and it's unnecessary here
> > > because platform_device_register_full() does not ret
On Mon, Nov 07, 2016 at 07:57:11PM +0100, Geert Uytterhoeven wrote:
> Hi Konrad,
>
> On Mon, Oct 31, 2016 at 6:52 PM, Konrad Rzeszutek Wilk
> wrote:
> > On Mon, Oct 31, 2016 at 04:45:04PM +0100, Geert Uytterhoeven wrote:
> >> On architectures like arm64, swiotlb is tied intimately to the core
> >
Hi Konrad,
On Mon, Oct 31, 2016 at 6:52 PM, Konrad Rzeszutek Wilk
wrote:
> On Mon, Oct 31, 2016 at 04:45:04PM +0100, Geert Uytterhoeven wrote:
>> On architectures like arm64, swiotlb is tied intimately to the core
>> architecture DMA support. In addition, ZONE_DMA cannot be disabled.
>>
>> To aid
Hook up the Audio-DMAC and sound device nodes to the SYSC "always-on" PM
Domain, for a more consistent device-power-area description in DT.
Cfr. commit 0761ff2ad0c581f3 ("ARM: dts: r8a7794: Add SYSC PM Domains").
Fixes: 320d6c5a08a4abd3 ("ARM: dts: r8a7794: add sound support")
Fixes: 298e4ee3d213
The parent clock of the HSUSB clock is the HP clock, not the MP clock.
Fixes: c7bab9f929e51761 ("ARM: shmobile: r8a7794: Add USB clocks to device
tree")
Signed-off-by: Geert Uytterhoeven
---
arch/arm/boot/dts/r8a7794.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/
On Wed, Oct 26, 2016 at 4:14 PM, Ulrich Hecht
wrote:
> Signed-off-by: Ulrich Hecht
> Reviewed-by: Geert Uytterhoeven
> ---
> arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 12
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.d
On 12 September 2016 at 16:15, Chris Brandt wrote:
> For the most part, the SDHI controller in the RZ/A1 (r7s72100)
> is the same as other Renesas SoC...except for the fact that the
> data port register was widened to 32-bits and the 16-bit accesses
> in the current tmio driver aren't going to cut
On Wed, Nov 2, 2016 at 10:57 PM, Sergei Shtylyov
wrote:
> Add macros usable by the device tree sources to reference the R8A7743 CPG
> clocks by index. The data comes from the table 7.2b in the revision 0.50
> of the RZ/G Series User's Manual.
>
> Signed-off-by: Sergei Shtylyov
> Reviewed-by: G
On Mon, Nov 7, 2016 at 9:34 AM, Geert Uytterhoeven wrote:
> On Sat, Nov 5, 2016 at 11:31 PM, Sergei Shtylyov
> wrote:
>> Add macros usable by the device tree sources to reference the R8A7745 CPG
>> clocks by index. The data comes from the table 7.2c in the revision 0.50
>> of the RZ/G Series U
On Mon, Nov 07, 2016 at 10:35:31AM +0100, Geert Uytterhoeven wrote:
> On Mon, Oct 31, 2016 at 12:30 PM, Geert Uytterhoeven
> wrote:
> > Some Renesas SoCs may exist in different revisions, providing slightly
> > different functionalities (e.g. R-Car H3 ES1.x and ES2.0), and behavior
> > (errate and
Hi Geert,
On 07/11/16 15:41, Geert Uytterhoeven wrote:
> Hi Robin,
>
> On Tue, Nov 1, 2016 at 12:46 PM, Robin Murphy wrote:
> To aid debugging and catch devices not supporting DMA to memory outside
> the 32-bit address space, add a kernel command line option
> "swiotlb=nobounce", whi
On Wed, Nov 2, 2016 at 2:23 PM, Niklas Söderlund
wrote:
> Add the SoC specific information for Renesas Salvator-X M3 (r8a7796)
> board.
Same comments as for patch 31/32.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m
From: Takatoshi Akiyama
While spin is already locked, serial output request causes the deadlock,
because serial output process also tries to lock the spin.
This patch removes serial output with spin locked.
Signed-off-by: Takatoshi Akiyama
Signed-off-by: Takeshi Kihara
Signed-off-by: Simon Hor
On Mon, Nov 07, 2016 at 04:42:53PM +0100, Simon Horman wrote:
> From: Takatoshi Akiyama
>
> The SCSCR register access in sci_break_ctl() is not locked.
>
> sci_start_tx() and sci_set_termios() changes the SCSCR register,
> but does not lock sci_port.
Maybe naive question: Shouldn't stop_tx and/
On Wed, Nov 2, 2016 at 2:23 PM, Niklas Söderlund
wrote:
> Add the SoC specific information for Renesas Salvator-X H3 (r8a7795)
> board.
Salvator-X is the board, while the support you add is purely SoC-specific.
> Signed-off-by: Niklas Söderlund
> ---
> drivers/media/platform/rcar-vin/Kconfig
Hi Simon,
On Mon, Nov 7, 2016 at 3:07 PM, Simon Horman wrote:
> From: Ryo Kataoka
>
> MSIOF Base Address H'E6xx can be accessed by CPU and DMAC.
> MSIOF Base Address H'E7xx for DMAC was removed from H/W manual.
>
> Fixes: b0d0ce8b6b91 ("spi: sh-msiof: Add DMA support")
> Signed-off-by: Ryo K
On Mon, Nov 07, 2016 at 04:42:39PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Mon, Nov 7, 2016 at 4:40 PM, Simon Horman wrote:
> > On Mon, Nov 07, 2016 at 04:20:56PM +0100, Geert Uytterhoeven wrote:
> >> On Mon, Nov 7, 2016 at 4:14 PM, Simon Horman
> >> wrote:
> >> > From: Takatoshi Ak
On Mon, Nov 07, 2016 at 04:33:34PM +0100, Simon Horman wrote:
> From: Masaharu Hayakawa
>
> The problem which the card inserted in the slot of SDHI{0,3} does not
> recognize in the combination of some boards and UHS-I sdcard occurred.
>
> Therefore, this patch repealed SDR104 of SDHI0 and SDHI3.
Hi Mike, Stephen,
The following changes since commit dbdcc4f996df280eb2758095b4774ea62da8a2a7:
clk: renesas: r8a7796: Add DU and LVDS clocks (2016-11-02 20:40:08 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
t
Hi Simon,
On Mon, Nov 7, 2016 at 4:40 PM, Simon Horman wrote:
> On Mon, Nov 07, 2016 at 04:20:56PM +0100, Geert Uytterhoeven wrote:
>> On Mon, Nov 7, 2016 at 4:14 PM, Simon Horman
>> wrote:
>> > From: Takatoshi Akiyama
>> >
>> > While spin is already locked, serial output request causes the de
From: Takatoshi Akiyama
The SCSCR register access in sci_break_ctl() is not locked.
sci_start_tx() and sci_set_termios() changes the SCSCR register,
but does not lock sci_port.
Therefore, this patch adds lock during register access.
Also, remove the log output that leads to a double lock.
Sig
Hi Robin,
On Tue, Nov 1, 2016 at 12:46 PM, Robin Murphy wrote:
To aid debugging and catch devices not supporting DMA to memory outside
the 32-bit address space, add a kernel command line option
"swiotlb=nobounce", which disables the use of bounce buffers.
If specified, trying
On Mon, Nov 07, 2016 at 04:20:56PM +0100, Geert Uytterhoeven wrote:
> On Mon, Nov 7, 2016 at 4:14 PM, Simon Horman
> wrote:
> > From: Takatoshi Akiyama
> >
> > While spin is already locked, serial output request causes the deadlock,
> > because serial output process also tries to lock the spin.
On Mon, Nov 07, 2016 at 04:26:18PM +0100, Wolfram Sang wrote:
> On Mon, Nov 07, 2016 at 04:14:41PM +0100, Simon Horman wrote:
> > From: Takatoshi Akiyama
> >
> > While spin is already locked, serial output request causes the deadlock,
> > because serial output process also tries to lock the spin.
Hi Linus,
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
tags/sh-pfc-for-v4.10-tag1
for you to fe
Hi Mike, Stephen,
The following changes since commit 1001354ca34179f3db924eb66672442a173147dc:
Linux 4.9-rc1 (2016-10-15 12:17:50 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
tags/clk-renesas-for-v4.10-tag1
From: Masaharu Hayakawa
The problem which the card inserted in the slot of SDHI{0,3} does not
recognize in the combination of some boards and UHS-I sdcard occurred.
Therefore, this patch repealed SDR104 of SDHI0 and SDHI3.
Signed-off-by: Masaharu Hayakawa
Signed-off-by: Takeshi Kihara
---
ar
From: Kazuya Mizuguchi
The kernel panic occurs with "swiotlb buffer is full" message
after repeating suspend and resume, because dma_map_single of
ravb_ring_format and ravb_start_xmit is not released.
This patch adds dma_unmap_single in ravb_ring_free, and fixes
its problem.
Signed-off-by: Kazuy
On Mon, Nov 07, 2016 at 04:14:41PM +0100, Simon Horman wrote:
> From: Takatoshi Akiyama
>
> While spin is already locked, serial output request causes the deadlock,
> because serial output process also tries to lock the spin.
> This patch removes serial output with spin locked.
>
> Signed-off-by
On Mon, Nov 7, 2016 at 4:14 PM, Simon Horman wrote:
> From: Takatoshi Akiyama
>
> While spin is already locked, serial output request causes the deadlock,
> because serial output process also tries to lock the spin.
> This patch removes serial output with spin locked.
>
> Signed-off-by: Takatoshi
From: Takatoshi Akiyama
While spin is already locked, serial output request causes the deadlock,
because serial output process also tries to lock the spin.
This patch removes serial output with spin locked.
Signed-off-by: Takatoshi Akiyama
Signed-off-by: Takeshi Kihara
Signed-off-by: Simon Hor
On Mon, Nov 07, 2016 at 03:50:00AM +, Kuninori Morimoto wrote:
>
> Hi Russell
>
> > > + platform = platform_device_register_full(&pdevinfo);
> > > + if (IS_ERR_OR_NULL(platform))
> > > + return PTR_ERR(platform);
> >
> > This is wrong. If platform is NULL, PTR_ERR() will return zero
Hi Simon,
On Mon, Nov 7, 2016 at 3:07 PM, Simon Horman wrote:
> From: Hiromitsu Yamasaki
>
> DMA supports 32-bit words only,
> even if BITLEN1 of SITMDR2 register is 16bit.
>
> Fixes: b0d0ce8b6b91 ("spi: sh-msiof: Add DMA support")
> Signed-off-by: Hiromitsu Yamasaki
> Signed-off-by: Simon Horm
From: Hiromitsu Yamasaki
DMA supports 32-bit words only,
even if BITLEN1 of SITMDR2 register is 16bit.
Fixes: b0d0ce8b6b91 ("spi: sh-msiof: Add DMA support")
Signed-off-by: Hiromitsu Yamasaki
Signed-off-by: Simon Horman
---
Geert, this is a patch from the Gen3 BSP 3.3.2 kernel.
Please consider
From: Ryo Kataoka
MSIOF Base Address H'E6xx can be accessed by CPU and DMAC.
MSIOF Base Address H'E7xx for DMAC was removed from H/W manual.
Fixes: b0d0ce8b6b91 ("spi: sh-msiof: Add DMA support")
Signed-off-by: Ryo Kataoka
Signed-off-by: Hiromitsu Yamasaki
Signed-off-by: Simon Horman
---
On Mon, Nov 07, 2016 at 01:32:28PM +, Phil Edworthy wrote:
> Hi Simon,
>
> On 07 November 2016 12:01, Simon Horman wrote:
> > From: Phil Edworthy
> >
> > Signed-off-by: Phil Edworthy
> > Signed-off-by: Simon Horman
> > ---
> >
> > Phil, this is from the 3.3.2 BSP.
> > Is it appropriate fo
On Thu, Nov 03, 2016 at 09:06:15PM +0300, Vladimir Barinov wrote:
> Hello,
>
> This adds the folowing:
> - R8A7796 SoC based M3ULCB (R-Car Starter Kit Pro) device tree
> - Document DT bindings
>
> Vladimir Barinov (9):
> [1/9] dt: arm: shmobile: add M3ULCB board DT bindings
I took the liberty of
Hi Simon,
On 07 November 2016 12:01, Simon Horman wrote:
> From: Phil Edworthy
>
> Signed-off-by: Phil Edworthy
> Signed-off-by: Simon Horman
> ---
>
> Phil, this is from the 3.3.2 BSP.
> Is it appropriate for mainline?
No, this is not for upstream. The pci_fixup_irqs_local function was an RF
On Thu, Nov 03, 2016 at 09:04:44PM +0300, Vladimir Barinov wrote:
> This updates H3ULCB Device tree bindings Documentation with
> official board name
>
> Signed-off-by: Vladimir Barinov
Thanks, I have queued this up after updating the subject to:
arm64: dts: h3ulcb: update documentation with of
On Thu, Nov 03, 2016 at 09:04:54PM +0300, Vladimir Barinov wrote:
> This updates H3ULCB device tree header with official board name
>
> Signed-off-by: Vladimir Barinov
Thanks, I have queued this up.
On Thu, Nov 03, 2016 at 09:05:02PM +0300, Vladimir Barinov wrote:
> This supports SDHI2 for H3ULCB onboard eMMC
>
> Signed-off-by: Vladimir Barinov
> ---
> arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 43
> ++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch
Hi Simon,
On 07.11.2016 16:00, Simon Horman wrote:
On Thu, Nov 03, 2016 at 09:07:51PM +0300, Vladimir Barinov wrote:
This supports SDHI0 on M3ULCB board SD card slot
Is SDHI3 also exposed on the M3ULCB?
No, SDHI3 is not exposed on M3ULCB.
Only SDHI0 exposed to SD slot and SDHI2 as eMMC.
If
On Sun, Nov 6, 2016 at 9:20 PM, Wolfram Sang
wrote:
> Some drivers like i2c-gpio do not have dedicated pinctrl states. They
> broke when error checking for pinctrl was added. Detect them now, and in
> their case, simply skip over pinctrl configuration.
>
> Signed-off-by: Wolfram Sang
> ---
> dri
On Sun, Nov 6, 2016 at 9:20 PM, Wolfram Sang
wrote:
> From: Simon Horman
>
> The rename from i2cexio to i2cexio0 is in in preparation for adding
double "in"
> i2cexio1 which will use the dmuxer for IIC1/I2C1.
demuxer
> The reindexing from i2c8 to i2c10 is to allow space for grouping of
> addi
Hi Simon,
On 07.11.2016 15:57, Simon Horman wrote:
On Thu, Nov 03, 2016 at 09:07:31PM +0300, Vladimir Barinov wrote:
This supports GPIO leds on M3ULCB board
Are GPIO leds and keys also present on the H3ULCB.
Yes.
If so could you consider sending patches to enable them?
H3ULCB already includ
On Thu, Nov 03, 2016 at 09:07:51PM +0300, Vladimir Barinov wrote:
> This supports SDHI0 on M3ULCB board SD card slot
Is SDHI3 also exposed on the M3ULCB?
If so could you consider sending patches to enable it?
> Signed-off-by: Vladimir Barinov
> ---
> arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.d
On Thu, Nov 03, 2016 at 09:07:31PM +0300, Vladimir Barinov wrote:
> This supports GPIO leds on M3ULCB board
Are GPIO leds and keys also present on the H3ULCB.
If so could you consider sending patches to enable them?
> Signed-off-by: Vladimir Barinov
> ---
> arch/arm64/boot/dts/renesas/r8a7796-m
Hi Niklas,
On Wed, Nov 2, 2016 at 2:22 PM, Niklas Söderlund
wrote:
> A V4L2 driver for Renesas R-Car MIPI CSI-2 interface. The driver
> supports the rcar-vin driver on R-Car Gen3 SoCs where a separate driver
> is needed to receive CSI-2.
>
> Driver is based on a prototype by Koji Matsuoka in the
On Wed, Nov 2, 2016 at 2:23 PM, Niklas Söderlund
wrote:
> Document the Gen3 devicetree bindings. The new bindings are all handled
> in the port@1 node, if a endpoint is described as on Gen2 in port@0 the
an endpoint
> driver will work in Gen2 mode and this is supported on Gen3. The new
> CSI-2 v
On Wed, Nov 2, 2016 at 2:23 PM, Niklas Söderlund
wrote:
> When Gen3 support is added to the driver more then chip id will be
> different for the different Soc. To avoid a lot of if statements in the
> code create a struct chip_info to contain this information.
>
> Signed-off-by: Niklas Söderlund
On Fri, Nov 04, 2016 at 02:43:18PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 11/3/2016 10:34 PM, Jacopo Mondi wrote:
>
> >Update the PFC pin groups and function names of DU interface for
> >r8a7794 ALT board.
> >
> >The currently specified pin groups and function names prevented PFC and
> >DU
On Tue, Oct 25, 2016 at 12:49:42PM +0200, Geert Uytterhoeven wrote:
> On Tue, Sep 13, 2016 at 12:57 PM, Simon Horman
> wrote:
> > Add the sd-uhs-sdr104 property to SDHI0 and SDHI1.
>
> SDHI0 and SDHI3.
Thanks, I will fix that.
On Tue, Oct 25, 2016 at 12:48:40PM +0200, Geert Uytterhoeven wrote:
> On Tue, Sep 13, 2016 at 12:57 PM, Simon Horman
> wrote:
> > Add the sd-uhs-sdr104 property to SDHI0 and SDHI1.
>
> SDHI0 and SDHI3?
Thanks, I will fix that.
On Wed, Oct 26, 2016 at 04:14:04PM +0200, Ulrich Hecht wrote:
> Hi!
>
> This revision is based on renesas-devel-20161024-v4.9-rc2. It adds the
> Reviewed-bys and the entries for SYS-DMAC2 in the applicable I2C nodes. I
> have also made sure it works with 64-bit memory enabled.
>
> CU
> Uli
>
>
Hi Uli,
On Thu, Sep 15, 2016 at 8:55 PM, Geert Uytterhoeven
wrote:
> On Wed, Sep 14, 2016 at 6:47 PM, Ulrich Hecht
> wrote:
>> Signed-off-by: Ulrich Hecht
>> ---
>> drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 255
>> +++
>> 1 file changed, 255 insertions(+)
>>
>> di
On 2016-11-07 11:57:36 +0100, Geert Uytterhoeven wrote:
> On Thu, Nov 3, 2016 at 6:10 PM, Laurent Pinchart
> wrote:
> > On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
> >> There is a bug in the r8a7795 bias code where a WARN() is trigged
> >> anytime a pin from PUEN0/PUD0is accessed.
> >
Hi Hiep,
On Mon, Nov 7, 2016 at 11:37 AM, Hiep Cao Minh wrote:
> On 11/07/2016 06:44 PM, Geert Uytterhoeven wrote:
>> On Fri, Sep 30, 2016 at 12:05 PM, Hiep Cao Minh
>> wrote:
>>
>> The issue you're seeing is due to a combination of commits
>> 5f3bca0db8ac01a7
>> ("ARM: shmobile:
On Mon, Nov 07, 2016 at 01:00:48PM +0100, Simon Horman wrote:
> From: Phil Edworthy
>
> Signed-off-by: Phil Edworthy
> Signed-off-by: Simon Horman
> ---
>
> Phil, this is from the 3.3.2 BSP.
> Is it appropriate for mainline?
I see there is also an infrastructure patch (by you) required for th
From: Phil Edworthy
Signed-off-by: Phil Edworthy
Signed-off-by: Simon Horman
---
Phil, this is from the 3.3.2 BSP.
Is it appropriate for mainline?
---
drivers/pci/host/pcie-rcar.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/ho
Hi Sergei,
On Wed, Nov 2, 2016 at 10:59 PM, Sergei Shtylyov
wrote:
> Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Based on the proof-of-concept R8A7791 CPG/MSSR patch by G
On Thu, Nov 3, 2016 at 5:06 PM, Ulrich Hecht
wrote:
> Thank you. Please check branch r8a7796-dmac-v2 at
> https://github.com/uli/kernel.git, that should contain everything you
> need.
FWIW, git://github.com/uli/kernel.git is much faster.
Gr{oetje,eeting}s,
Geert
--
Geer
Hi Hiep,
On Mon, Nov 7, 2016 at 2:00 AM, Cao Minh Hiep wrote:
> From: Hiep Cao Minh
>
> This patch rewrites the name of rspi_pio_transfer_in_or_out
> function.
>
> Signed-off-by: Hiep Cao Minh
Acked-by: Geert Uytterhoeven
But you want to use proper prefixes matching the style of the subsyste
On Fri, Nov 4, 2016 at 2:58 PM, Simon Horman wrote:
> From: Takeshi Kihara
>
> Correct HDMI parent clock so that the rate of the
> HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
> as per the v0.52 (Jun, 15) manual.
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Simon Horman
Reviewed
On Thu, Nov 3, 2016 at 6:10 PM, Laurent Pinchart
wrote:
> On Thursday 03 Nov 2016 16:34:21 Niklas Söderlund wrote:
>> There is a bug in the r8a7795 bias code where a WARN() is trigged
>> anytime a pin from PUEN0/PUD0is accessed.
>>
>> # cat /sys/kernel/debug/pinctrl/e606.pfc/pinconf-pins
>>
>
Hi Niklas,
On Thu, Nov 3, 2016 at 5:15 PM, Niklas Söderlund
wrote:
> There are pins on the r8a7795 which are not part of a GPIO bank nor
> can be muxed between different functions. They do however allow for the
> drive-strength to be configured. Add those pins to the list of pins and
> to the dri
Hi Geert
On 11/07/2016 06:44 PM, Geert Uytterhoeven wrote:
Hi Hiep,
On Fri, Sep 30, 2016 at 12:05 PM, Hiep Cao Minh wrote:
The issue you're seeing is due to a combination of commits
5f3bca0db8ac01a7
("ARM: shmobile: apmu: Add APMU DT support via Enable method") and
dc378795156d980c ("ARM: dts
Hello.
On 11/7/2016 1:09 PM, Geert Uytterhoeven wrote:
Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software
Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
(and RZ/G) code.
Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
.
On Thu, Nov 3, 2016 at 4:34 PM, Niklas Söderlund
wrote:
> Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
> when examining /sys/kernel/debug/pinctrl/e606.pfc/pinconf-pins if
> the operation get_bias() are implemented but the pin are not handled by
is implemented
is not
On Sat, Nov 05, 2016 at 12:45:02PM +0100, Wolfram Sang wrote:
>
> > To aid review the following git branches are provided:
> > * This patchset:
> > https:://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git
> > topic/sdr104-integration-v8
> > * This patch-set and above dependency
> >
Hi Hiep,
On Fri, Sep 30, 2016 at 12:05 PM, Hiep Cao Minh wrote:
The issue you're seeing is due to a combination of commits
5f3bca0db8ac01a7
("ARM: shmobile: apmu: Add APMU DT support via Enable method") and
dc378795156d980c ("ARM: dts: r8a7790: Add APMU nodes").
When
On Mon, Oct 31, 2016 at 12:30 PM, Geert Uytterhoeven
wrote:
> Some Renesas SoCs may exist in different revisions, providing slightly
> different functionalities (e.g. R-Car H3 ES1.x and ES2.0), and behavior
> (errate and quirks). This needs to be catered for by drivers and/or
> platform code. Th
Hi Stephen,
On Fri, Nov 4, 2016 at 8:49 PM, Stephen Boyd wrote:
> On 11/02, Geert Uytterhoeven wrote:
>> On Tue, Nov 1, 2016 at 12:25 AM, Stephen Boyd wrote:
>> >
>> > Would the pull requests for clk also have dts changes at the base
>> > of the tree? Perhaps clk side can just ack the clk patche
Hi Sergei,
On Sat, Nov 5, 2016 at 11:34 PM, Sergei Shtylyov
wrote:
> Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Based on the proof-of-concept R8A7791 CPG/MSSR patch by G
Hi Sergei,
On Sat, Nov 5, 2016 at 11:31 PM, Sergei Shtylyov
wrote:
> Add macros usable by the device tree sources to reference the R8A7745 CPG
> clocks by index. The data comes from the table 7.2c in the revision 0.50
> of the RZ/G Series User's Manual.
>
> Signed-off-by: Sergei Shtylyov
> Re
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