Hello!
On 12/29/2016 11:45 PM, Nikita Yushchenko wrote:
It is possible that PCI device supports 64-bit DMA addressing, and thus
it's driver sets device's dma_mask to DMA_BIT_MASK(64), however PCI host
Its.
bridge has limitations on inbound transactions addressing. Example of
such setup i
On 12/30/2016 12:46 PM, Sergei Shtylyov wrote:
It is possible that PCI device supports 64-bit DMA addressing, and thus
it's driver sets device's dma_mask to DMA_BIT_MASK(64), however PCI host
Its.
bridge has limitations on inbound transactions addressing. Example of
such setup is NVME
On 13/12/16 12:37, Jacopo Mondi wrote:
> Add IIO driver for Maxim MAX11100 single-channel ADC.
> Add DT bindings documentation.
>
> Signed-off-by: Jacopo Mondi
A quick process related thing. Please don't post a new
version of a driver as a reply to an old version. It very rapidly
leads to deep a
On 13/12/16 15:53, Wolfram Sang wrote:
>
>>> +struct max11100_state {
>>> + const struct max11100_chip_desc *desc;
>>> + struct spi_device *spi;
>>> + int vref_uv;
>>
>> unsi
>> It's good practice to move the smaller members to the end of the structure,
>> to avoid gaps due to al
On 14/12/16 12:00, jac...@jmondi.org wrote:
> Hello Peter,
>thanks for review
>
> On 13/12/2016 21:33, Peter Meerwald-Stadler wrote:
>>
>>> Add IIO driver for Maxim MAX11100 single-channel ADC.
>>> Add DT bindings documentation.
>>
>> some more comments
>>
>>> Signed-off-by: Jacopo Mondi
>>>
On 13/12/16 12:37, Jacopo Mondi wrote:
> Add IIO driver for Maxim MAX11100 single-channel ADC.
> Add DT bindings documentation.
>
> Signed-off-by: Jacopo Mondi
Nothing significant to add, but a few comments inline.
Jonathan
> ---
>
> v1 -> v2:
> - incorporated pmeerw's review comments
>
