On Thu, Feb 02, 2017 at 04:20:00PM -0500, Chris Brandt wrote:
> This enables the 128KB L2 cache in the RZ/A1 (R7S72100).
>
> The 'Write full line of zeros mode' of this Cortex-A9 cannot be used
> because the sideband signals between the CA9 and PL310 are not connected.
> Since there is no option t
Hi Chris,
CC linux-arm-kernel
On Thu, Feb 2, 2017 at 10:20 PM, Chris Brandt wrote:
> This enables the 128KB L2 cache in the RZ/A1 (R7S72100).
>
> The 'Write full line of zeros mode' of this Cortex-A9 cannot be used
> because the sideband signals between the CA9 and PL310 are not connected.
> Sin
Hi Dong,
On Mon, Feb 6, 2017 at 2:02 AM, DongCV wrote:
> From: Dong
>
> This patch fixes the output warning logs and data loss when
> performing mount/umount then remount the device with jffs2 format.
>
> This is the warning logs when performing mount/umount then remount the device
> with jffs2
On Tue, Jan 31, 2017 at 12:17:07PM +0100, Geert Uytterhoeven wrote:
> Currently, the IPMMU/VMSA driver supports 32-bit I/O Virtual Addresses
> only, and thus sets io_pgtable_cfg.ias = 32. However, it doesn't force
> a 32-bit IOVA space through the IOMMU Domain Geometry.
>
> Hence if a device (e.g
From: Hiroyuki Yokoyama
This patch fixes the problem that occasionally released resources
before the end of interrupt processing.
[ 58.156412] Unable to handle kernel NULL pointer dereference at virtual
address
[ 58.166155] pgd = 8006f78b
[ 58.169822] [] *pgd=
On 02/06/2017 01:30 PM, Yoshihiro Shimoda wrote:
> From: Hiroyuki Yokoyama
>
> This patch fixes the problem that occasionally released resources
> before the end of interrupt processing.
>
> [ 58.156412] Unable to handle kernel NULL pointer dereference at virtual
> address
> [ 58.1
On Mon, Feb 06, 2017 at 10:02:13AM +0900, DongCV wrote:
> From: Dong
>
> This patch fixes the output warning logs and data loss when
> performing mount/umount then remount the device with jffs2 format.
This is not a good changelog since it does not describe what the problem
with the driver is or
Hi Simon,
On Monday, February 06, 2017, Simon Horman wrote:
> is it possible to apply the .dtsi and .c portions of this change
> separately and still get sane behaviour at each step?
>
> If so I would like to request that this patch be split into two patches,
> one for .c and one for .dtsi. This
Hi Geert,
On Monday, February 06, 2017, Geert Uytterhoeven wrote:
> CC linux-arm-kernel
>
> On Thu, Feb 2, 2017 at 10:20 PM, Chris Brandt
> wrote:
> > This enables the 128KB L2 cache in the RZ/A1 (R7S72100).
> >
> > The 'Write full line of zeros mode' of this Cortex-A9 cannot be used
> > because
Hi Chris,
On Mon, Feb 6, 2017 at 3:58 PM, Chris Brandt wrote:
> On Monday, February 06, 2017, Geert Uytterhoeven wrote:
>> CC linux-arm-kernel
>>
>> On Thu, Feb 2, 2017 at 10:20 PM, Chris Brandt
>> wrote:
>> > This enables the 128KB L2 cache in the RZ/A1 (R7S72100).
>> >
>> > The 'Write full lin
Hi Geert,
On Monday, February 06, 2017, Geert Uytterhoeven wrote:
> > I agree that faking out a secure write function just so the fill-zeros
> > sideband feature is not enabled is a bit of a hack, but I'm not sure
> > if modifying the cache-l2x0.c was an option.
>
> Given I've added "arm,shared-o
Hi Laurent,
On 01/02/2017 16:21, Laurent Pinchart wrote:
Hi Jacopo,
[snip]
+}
+
+/**
+ * rz_dt_node_to_map() - Parse device tree nodes and collect pins, groups
and
+ * functions
I don't think we have groups and functions, do we ?
Sort of.. The hardware does not hav
* jacopo mondi [170206 10:16]:
> Currently there is no generic pinctrl and pinmux function to retrieve a
> group or function by name, but only by their id (selector).
> It would take 10minutes to add them, but I wonder if that's desirable or
> there are other ways to do so I haven't found out yet.
Hi Lars,
> -Original Message-
> From: Lars-Peter Clausen [mailto:l...@metafoo.de]
> Sent: Monday, February 06, 2017 9:40 PM
>
> On 02/06/2017 01:30 PM, Yoshihiro Shimoda wrote:
> > From: Hiroyuki Yokoyama
> >
> > This patch fixes the problem that occasionally released resources
> > befor
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