Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

On Tue, Jul 4, 2017 at 10:20 PM, Krzysztof Kozlowski wrote: > On Tue, Jul 04, 2017 at 10:12:13PM +0200, Rafael J. Wysocki wrote: >> On Tue, Jul 4, 2017 at 10:05 PM, Krzysztof Kozlowski wrote: > >> >> > Thanks for report! >> >> >> > >> >> >> > Damn it, although

Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

On Tue, Jul 04, 2017 at 10:12:13PM +0200, Rafael J. Wysocki wrote: > On Tue, Jul 4, 2017 at 10:05 PM, Krzysztof Kozlowski wrote: >> >> > Thanks for report! > >> >> > > >> >> > Damn it, although I couldn't find this in the code, but I was fearing > >> >> > that this ends up in

Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

On Tue, Jul 4, 2017 at 10:05 PM, Krzysztof Kozlowski wrote: > On Tue, Jul 04, 2017 at 09:54:10PM +0200, Rafael J. Wysocki wrote: >> On Tue, Jul 4, 2017 at 8:36 PM, Krzysztof Kozlowski wrote: >> > On Tue, Jul 04, 2017 at 08:19:47PM +0200, Geert Uytterhoeven

Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

On Tue, Jul 04, 2017 at 09:54:10PM +0200, Rafael J. Wysocki wrote: > On Tue, Jul 4, 2017 at 8:36 PM, Krzysztof Kozlowski wrote: > > On Tue, Jul 04, 2017 at 08:19:47PM +0200, Geert Uytterhoeven wrote: > >> Hi Krzysztof, > >> > >> On Tue, Jul 4, 2017 at 8:10 PM, Krzysztof Kozlowski

Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

On Tue, Jul 4, 2017 at 8:36 PM, Krzysztof Kozlowski wrote: > On Tue, Jul 04, 2017 at 08:19:47PM +0200, Geert Uytterhoeven wrote: >> Hi Krzysztof, >> >> On Tue, Jul 4, 2017 at 8:10 PM, Krzysztof Kozlowski wrote: >> > On Tue, Jul 04, 2017 at 03:01:15PM +0200,

Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

On Tue, Jul 04, 2017 at 08:19:47PM +0200, Geert Uytterhoeven wrote: > Hi Krzysztof, > > On Tue, Jul 4, 2017 at 8:10 PM, Krzysztof Kozlowski wrote: > > On Tue, Jul 04, 2017 at 03:01:15PM +0200, Geert Uytterhoeven wrote: > >> On Wed, Jun 28, 2017 at 4:56 PM, Krzysztof Kozlowski

Architecture Timer on R-Car Gen2

Hi Magnus, Mar[ck], Simon, We're (finally) getting close to the point where Renesas R-Car Gen2 platform code no longer relies on hardcoded addresses. The remaining parts are related to the ARM Architecture Timer / Generic Timer / Generic Counter. More specifically the code in

Re: [PATCH 1/2] ARM: shmobile: Add CA7 arch_timer initialization for secondary CPUs

Hi Marc, On Tue, Jul 4, 2017 at 7:32 PM, Marc Zyngier wrote: > On 04/07/17 18:02, Geert Uytterhoeven wrote: >> On Cortex-A7, the arch timer CNTVOFF register is uninitialized. >> Hence when enabling SMP on r8a7794, the kernel log is spammed with: >> >> WARNING: Underflow

Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

Hi Krzysztof, On Tue, Jul 4, 2017 at 8:10 PM, Krzysztof Kozlowski wrote: > On Tue, Jul 04, 2017 at 03:01:15PM +0200, Geert Uytterhoeven wrote: >> On Wed, Jun 28, 2017 at 4:56 PM, Krzysztof Kozlowski wrote: >> > genpd_syscore_switch() had two problems: >> > 1.

Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

On Tue, Jul 04, 2017 at 03:01:15PM +0200, Geert Uytterhoeven wrote: > Hi Krzysztof, Rafael, > > On Wed, Jun 28, 2017 at 4:56 PM, Krzysztof Kozlowski wrote: > > genpd_syscore_switch() had two problems: > > 1. It silently assumed that device, it is being called for, belongs to > >

[PATCH/RFC 2/2] ARM: shmobile: rcar-gen2: Correct arch timer frequency on RZ/G1E

According to the datasheet, the frequency of the ARM architecture timer on RZ/G1E depends on the frequency of the ZS clock, just like on R-Car E2 and V2H. Signed-off-by: Geert Uytterhoeven --- Untested due to lack of hardware. ---

[PATCH/RFC 0/2] ARM: renesas: rcar-gen2: arch_timer cleanups

Hi Simon, Magnus, Sergei, This RFC patch series contains two small fixes for the ARM architecture timer initialization in platform code for Renesas R-Car Gen2 and RZ/G1 SoCs. - The first patch skips an unneeded initialization on R-Car V2h. This is marked RFC as the check for

Re: [PATCH 1/2] ARM: shmobile: Add CA7 arch_timer initialization for secondary CPUs

Hi Geert, On 04/07/17 18:02, Geert Uytterhoeven wrote: > On Cortex-A7, the arch timer CNTVOFF register is uninitialized. > Hence when enabling SMP on r8a7794, the kernel log is spammed with: > > WARNING: Underflow in clocksource 'arch_sys_counter' observed, time > update ignored. >

[PATCH 2/2] ARM: dts: r8a7794: Add SMP support

From: Sergei Shtylyov Add the device tree node for the Advanced Power Management Unit (APMU). Use the "enable-method" prop to point out that the APMU should be used for the SMP support. Signed-off-by: Sergei Shtylyov

[PATCH 0/2] ARM: renesas: Enable SMP on R-Car E2

Hi Magnus, Mar[ck], Sergei, Simon, This patch series enables SMP on R-Car E2 (r8a7794). - The first patch initializes CNTVOFF for secondary CPU cores, like is already done for the boot CPU core. Without this, the ARM arch timer doesn't work on secondary CPU cores. - The

[PATCH 1/2] ARM: shmobile: Add CA7 arch_timer initialization for secondary CPUs

On Cortex-A7, the arch timer CNTVOFF register is uninitialized. Hence when enabling SMP on r8a7794, the kernel log is spammed with: WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored. Please report this, consider using a different clocksource, if

Re: [PATCH 0/9] ARM: renesas: Use SMP jump stub SRAM region from DT

On Tue, Jul 4, 2017 at 5:41 PM, Geert Uytterhoeven wrote: > The R-Car Gen2 platform code for CPU core bringup needs to copy a jump > stub to on-SoC SRAM. Currently it uses a hardcoded address pointing to > ICRAM1. > > This patch series adds support to specify this region

[PATCH] ARM: dts: r8a7743: Add GPIO support

Describe GPIO blocks in the R8A7743 device tree. Signed-off-by: Biju Das <biju@bp.renesas.com> Reviewed-by: Chris Paterson <chris.paters...@renesas.com> --- This patch is been tested against linux-next tag next-20170704. It depends upon the patch 1)https://www.mail-archive.com/l

[PATCH 1/9] dt-bindings: sram: Document renesas,smp-sram

Document reserved SRAM for the SMP jump stub on Renesas R-Car Gen2 and RZ/G1 SoCs. Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/sram/renesas,smp-sram.txt | 27 ++ 1 file changed, 27 insertions(+) create mode 100644

[PATCH 6/9] ARM: dts: r8a7791: Reserve SRAM for the SMP jump stub

Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index

[PATCH 4/9] ARM: dts: r8a7745: Reserve SRAM for the SMP jump stub

Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7745.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index

[PATCH 5/9] ARM: dts: r8a7790: Reserve SRAM for the SMP jump stub

Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index

[PATCH 8/9] ARM: dts: r8a7793: Reserve SRAM for the SMP jump stub

Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7793.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index

[PATCH 0/9] ARM: renesas: Use SMP jump stub SRAM region from DT

Hi Magnus, Mark, Rob, Simon, The R-Car Gen2 platform code for CPU core bringup needs to copy a jump stub to on-SoC SRAM. Currently it uses a hardcoded address pointing to ICRAM1. This patch series adds support to specify this region from DT. It consists of 3 parts: - DT binding

[PATCH 7/9] ARM: dts: r8a7792: Reserve SRAM for the SMP jump stub

Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7792.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index

[PATCH 3/9] ARM: dts: r8a7743: Reserve SRAM for the SMP jump stub

Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7743.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index

[PATCH 2/9] ARM: shmobile: rcar-gen2: Obtain jump stub region from DT

Add support for obtaining from DT the SRAM region to store the jump stub for CPU core bringup, according to the renesas,smp-sram DT bindings. If no region is specified in DT, the code falls back to hardcoded ICRAM1 as before, to maintain backwards compatibility. Signed-off-by: Geert Uytterhoeven

[PATCH 9/9] ARM: dts: r8a7794: Reserve SRAM for the SMP jump stub

Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index

[PATCH 2/7] ARM: dts: r8a7745: Add Inter Connect RAM

RZ/G1E has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB). Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7745.dtsi | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index

[PATCH 3/7] ARM: dts: r8a7790: Add Inter Connect RAM

R-Car H2 has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7790.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index

[PATCH 6/7] ARM: dts: r8a7793: Add Inter Connect RAM

R-Car M2-N has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7793.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index

[PATCH 5/7] ARM: dts: r8a7792: Add Inter Connect RAM

R-Car V2H has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7792.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index

[PATCH 0/7] ARM: dts: renesas: Add Inter Connect RAM

Hi Simon, Magnus, R-Car Gen2 and RZ/G1 SoCs contain two or three blocks of SRAM, which can be used for several purposes. One such purpose is holding a jump stub for CPU core bringup. This patch series adds the SRAM blocks to the various DTS files, following the generic DT bindings for

[PATCH 7/7] ARM: dts: r8a7794: Add Inter Connect RAM

R-Car E2 has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index

[PATCH 1/7] ARM: dts: r8a7743: Add Inter Connect RAM

RZ/G1M has 3 regions of Inter Connect RAM (72 + 4 + 256 KiB). Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7743.dtsi | 15 +++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index

[PATCH 4/7] ARM: dts: r8a7791: Add Inter Connect RAM

R-Car M2-W has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7791.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index

Re: [RFT] mmc: tmio: fix CMD12 (STOP) handling

Hi Wolfram, On Mon, Jul 3, 2017 at 9:28 PM, Wolfram Sang wrote: > I always anticipated this code to be not correct, but now I had a test > case to prove it. According to all documentation I have, setting the > TMIO_STOP_STP bit ever only worked during block

renesas-drivers-2017-07-04-v4.12

I have pushed renesas-drivers-2017-07-04-v4.12 to https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git This tree is meant to ease development of platform support and drivers for Renesas ARM SoCs. It is created by merging (a) the for-next branches of various subsystem trees and

Re: [PATCH v3 2/8] PM / Domains: Handle safely genpd_syscore_switch() call on non-genpd device

Hi Krzysztof, Rafael, On Wed, Jun 28, 2017 at 4:56 PM, Krzysztof Kozlowski wrote: > genpd_syscore_switch() had two problems: > 1. It silently assumed that device, it is being called for, belongs to >generic power domain and used container_of() on its power domain >

Re: [RFT] mmc: tmio: fix CMD12 (STOP) handling

On Mon, Jul 03, 2017 at 09:28:23PM +0200, Wolfram Sang wrote: > I always anticipated this code to be not correct, but now I had a test > case to prove it. According to all documentation I have, setting the > TMIO_STOP_STP bit ever only worked during block transfers. This bit is > like manually

Re: Clocks used by another OS/CPU (was: Re: [RFC PATCH] clk: renesas: cpg-mssr: Add interface for critical core clocks)

On 04/07/17 08:31, Peter De Schrijver wrote: > On Mon, Jul 03, 2017 at 10:17:22AM +0100, Sudeep Holla wrote: >> >> >> On 01/07/17 19:14, Uwe Kleine-König wrote: >>> Hello, >>> >>> On Sat, Jul 01, 2017 at 07:02:48AM +0200, Dirk Behme wrote: >> >> [...] >> The other problem is

Re: Clocks used by another OS/CPU (was: Re: [RFC PATCH] clk: renesas: cpg-mssr: Add interface for critical core clocks)

On Mon, Jul 03, 2017 at 10:17:22AM +0100, Sudeep Holla wrote: > > > On 01/07/17 19:14, Uwe Kleine-König wrote: > > Hello, > > > > On Sat, Jul 01, 2017 at 07:02:48AM +0200, Dirk Behme wrote: > > [...] > > >> > >> > >> The other problem is security related. If, at all, you have to do it the >