Add pin configuration for Ethernet.
Signed-off-by: Chris Brandt
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts
b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index 5fac0f82d742..cedf887e8
Now that the RZ/A1 pin control driver has appeared in 4.13-rc1, it
is safe to now add pin configurations for RZ/A1 boards.
Chris Brandt (4):
arm: dts: rskrza1: Add SCIF2 pin group
arm: dts: rskrza1: Add Ethernet pin group
arm: dts: rskrza1: Add SDHI1 pin group
arm: dts: rskrza1: Add LED0
Add pin configuration for LED0 which is connected to a GPIO.
Signed-off-by: Chris Brandt
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts
b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index f8285b951140.
Add pin configuration for SDHI ch1.
Signed-off-by: Chris Brandt
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts
b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index cedf887e809a..f8285b951140 100644
Add pin configuration for SCIF2 serial console interface.
Signed-off-by: Chris Brandt
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts
b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index 72df20a04320..
Em Wed, 12 Jul 2017 01:29:42 +0300
Laurent Pinchart escreveu:
> From: Kieran Bingham
>
> The driver recently switched from handling page flip completion in the
> DU vertical blanking handler to the VSP frame end handler to fix a race
> condition. This unfortunately resulted in incorrect timesta
On Thu, Jul 20, 2017 at 6:15 AM, Mauro Carvalho Chehab
wrote:
> Em Wed, 19 Jul 2017 11:02:01 -0500
> Rob Herring escreveu:
>
>> On Wed, Jul 19, 2017 at 4:41 AM, Sylwester Nawrocki
>> wrote:
>> > On 07/18/2017 11:43 PM, Rob Herring wrote:
>> >> Now that we have a custom printf format specifier, c
Em Mon, 26 Jun 2017 21:12:23 +0300
Laurent Pinchart escreveu:
> The VSP supports both header and headerless display lists. The latter is
> easier to use when the VSP feeds data directly to the DU in continuous
> mode, and the driver thus uses headerless display lists for DU operation
> and header
Em Mon, 26 Jun 2017 21:12:22 +0300
Laurent Pinchart escreveu:
> The R-Car H3 ES2.0 VSP-DL instance has two LIF entities and can drive
> two display pipelines at the same time. Refactor the VSP DRM code to
> support that by introducing a vsp_drm_pipeline object that models one
> display pipeline.
Em Thu, 13 Jul 2017 18:57:40 +0100
Kieran Bingham escreveu:
> Hi Laurent,
>
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The VSP2-DL instance (present in the H3 ES2.0 and M3-N SoCs) has two LIF
> > instances. Adapt the driver infrastructure to support multiple LIFs.
> > Support for multiple
Em Fri, 14 Jul 2017 03:35:57 +0300
Laurent Pinchart escreveu:
> New Gen3 SoCs come with two new VSP2 variants names VSP2-BS and VSP2-DL,
> as well as a new VSP2-D variant on V3M and V3H SoCs. Add new entries for
> them in the VSP device info table.
>
> Signed-off-by: Laurent Pinchart
> Reviewed
Em Thu, 13 Jul 2017 14:38:40 +0100
Kieran Bingham escreveu:
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The Blend/ROP Sub Unit (BRS) is a stripped-down version of the BRU found
> > in several VSP2 instances. Compared to a regular BRU, it supports two
> > inputs only, and thus has no ROP unit
Em Fri, 14 Jul 2017 02:04:06 +0300
Laurent Pinchart escreveu:
> On Thursday 13 Jul 2017 14:16:03 Kieran Bingham wrote:
> > On 26/06/17 19:12, Laurent Pinchart wrote:
> > > In the H3 ES2.0 SoC the VSP2-DL instance has two connections to DU
> > > channels that need to be configured independently.
Em Thu, 13 Jul 2017 14:06:04 +0100
Kieran Bingham escreveu:
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > When the VSP1 is used in a DRM pipeline the driver doesn't register the
> > media device. Links between entities are not exposed to userspace, but
> > are still used internally for the sol
On Tue, Jul 18, 2017 at 04:43:04PM -0500, Rob Herring wrote:
> Now that we have a custom printf format specifier, convert users of
> full_name to use %pOF instead. This is preparation to remove storing
> of the full path string for each node.
>
> Signed-off-by: Rob Herring
Hi Rob,
Thanks for sen
Em Thu, 13 Jul 2017 14:00:31 +0100
Kieran Bingham escreveu:
> Hi Laurent,
>
> This looks like a good simplification/removal of obfuscation to me!
>
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The internal VSP entity source and sink pointers are stored as
> > media_entity pointers, which ar
Em Thu, 13 Jul 2017 13:50:20 +0100
Kieran Bingham escreveu:
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The sink pointer is used to configure routing inside the VSP, and as
> > such must point to the next VSP entity in the pipeline. The WPF being a
> > pipeline terminal sink, its output rout
Em Thu, 13 Jul 2017 18:02:20 +0100
Kieran Bingham escreveu:
> Hi Laurent,
>
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > When the display start interrupt occurs, we know that the hardware has
> > finished loading the active display list. The driver then proceeds to
> > recycle the list, assu
Em Thu, 13 Jul 2017 13:48:40 +0100
Kieran Bingham escreveu:
> Hi Laurent,
>
> Starts easy ... (I haven't gone through these in numerical order of course :D)
>
> On 26/06/17 19:12, Laurent Pinchart wrote:
> > The display list headers are filled using information from the display
> > list only. L
On Thu, Jul 20, 2017 at 2:54 PM, Geert Uytterhoeven
wrote:
> This patch series adds minimal support for the R-Car D3 SoC and the
> Draak development board, allowing to boot from a ramdisk using a serial
> console.
> arm64: dts: renesas: r8a77995: Use r8a7795-sysc binding definitions
> arm64:
Replace the hardcoded clock indices by R8A77995_CLK_* symbols.
Signed-off-by: Geert Uytterhoeven
---
This depends on "clk: renesas: Add r8a77995 CPG Core Clock Definitions".
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch
Replace the hardcoded power domain indices by R8A77995_PD_* symbols.
Signed-off-by: Geert Uytterhoeven
---
This depends on "soc: renesas: rcar-sysc: Add support for R-Car D3 power
areas".
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 ++-
1 file changed, 6 insertions(+), 5 deletions
Basic support for the Renesas Draak board based on R-Car D3:
- Memory,
- Main crystal,
- Serial console,
- Watchdog.
Signed-off-by: Geert Uytterhoeven
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 46 ++
Hi Simon, Magnus,
This patch series adds minimal support for the R-Car D3 SoC and the
Draak development board, allowing to boot from a ramdisk using a serial
console.
- The first two patches add DT sources for R-Car D3 and Draak.
Due to the use of hardcoded constants, they have no f
Basic support for the R-Car D3 SoC:
- PSCI,
- CPU,
- Cache controller,
- Main clocks and controller,
- Interrupt controller,
- Timer,
- Watchdog,
- PMU,
- Reset controller,
- Product register,
- System controller,
- UART for console.
Signed-off-by: Geert Uytterhoeven
---
T
Hi Mike, Stephen,
This patch series adds support for clocks on the R-Car D3 SoC.
As usual, this is meant to be queued up in clk-renesas-for-v4.14.
Thanks!
Geert Uytterhoeven (4):
clk: renesas: Add r8a77995 CPG Core Clock Definitions
clk: renesas: rcar-gen3: Add divider support for P
Add all R-Car D3 Clock Pulse Generator Core Clock Outputs, as listed
in Table 8.2f ("List of Clocks [R-Car D3]") of the R-Car Series, 3rd
Generation Hardware User's Manual (Rev. 0.55, Jun. 30, 2017).
Note that internal CPG clocks (S0, S1, S2, S3, S1C, S3C, SDSRC, and
SSPSRC) are not included, as t
On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one. Extend struct rcar_gen3_cpg_pll_config to handle
this. As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca.
Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 CPG code.
Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev.
0.55, Jun. 30, 2017.
Signed-off-by: Geert Uytterhoeven
Cc: devicet.
On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car
D3), a peripheral clock divider has been added, to select between clean
and spread spectrum parents.
Add a new clock type to the R-Car Gen3 driver core to handle this.
To avoid increasing the size of struct cpg_core_clk, both pa
Signed-off-by: Geert Uytterhoeven
---
drivers/soc/renesas/renesas-soc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/soc/renesas/renesas-soc.c
b/drivers/soc/renesas/renesas-soc.c
index ca26f13d399cf4c1..90d6b7a4340a6ee3 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/
Signed-off-by: Geert Uytterhoeven
Cc: devicet...@vger.kernel.org
---
.../bindings/power/renesas,rcar-sysc.txt | 1 +
drivers/soc/renesas/Kconfig| 5
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r8a77995-sysc.c
Add power domain indices for R-Car D3.
Signed-off-by: Geert Uytterhoeven
Cc: devicet...@vger.kernel.org
---
include/dt-bindings/power/r8a77995-sysc.h | 23 +++
1 file changed, 23 insertions(+)
create mode 100644 include/dt-bindings/power/r8a77995-sysc.h
diff --git a/include
Hi Simon, Magnus,
This patch series adds R-Car D3 support to the Renesas-specific SoC
drivers:
- SoC identification,
- System controller,
- Reset controller.
Thanks!
Geert Uytterhoeven (4):
soc: renesas: Identify R-Car D3
soc: renesas: Add r8a77995 SYSC PM Domain Binding Defini
Signed-off-by: Geert Uytterhoeven
Cc: devicet...@vger.kernel.org
---
Documentation/devicetree/bindings/reset/renesas,rst.txt | 1 +
drivers/soc/renesas/Kconfig | 2 +-
drivers/soc/renesas/rcar-rst.c | 1 +
3 files changed, 3 insertions(+), 1 de
Note that r8a77995 is the first Renesas "r8a" SoC matching against a 5
digit number, as r8a77990 will be a different SoC.
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindin
Signed-off-by: Geert Uytterhoeven
---
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt
b/Documentation/devicetree/bindings/arm/shmobile.txt
index 91f92d62650207fd..275cda1469b8b95c 100644
-
Hi Simon, Magnus, Rob, Mark, Catalin, Will,
This patch series adds base support for the Renesas R-Car D3 SoC and the
Renesas Draak development board.
It documents SoC and board specific DT compatible values, and adds a
Kconfig symbol.
Thanks!
Geert Uytterhoeven (3):
ARM: shmobile: Doc
Add a configuration option for the R-Car D3 SoC.
Note that r8a77995 is the first Renesas "r8a" SoC using a 5 digit
number in its Kconfig symbol, as r8a77990 will be a different SoC.
Signed-off-by: Geert Uytterhoeven
---
arch/arm64/Kconfig.platforms | 6 ++
1 file changed, 6 insertions(+)
d
On Tue, Jul 18, 2017 at 10:43 PM, Rob Herring wrote:
> Now that we have a custom printf format specifier, convert users of
> full_name to use %pOF instead. This is preparation to remove storing
> of the full path string for each node.
>
> Signed-off-by: Rob Herring
> Cc: Kyungmin Park
> Cc: Andr
Em Wed, 19 Jul 2017 11:02:01 -0500
Rob Herring escreveu:
> On Wed, Jul 19, 2017 at 4:41 AM, Sylwester Nawrocki
> wrote:
> > On 07/18/2017 11:43 PM, Rob Herring wrote:
> >> Now that we have a custom printf format specifier, convert users of
> >> full_name to use %pOF instead. This is preparatio
On Thu, Jul 20, 2017 at 11:53:39AM +0200, Maxime Ripard wrote:
> Hi Daniel,
>
> On Tue, Jul 18, 2017 at 09:35:03AM +0200, Daniel Vetter wrote:
> > On Tue, Jul 18, 2017 at 9:07 AM, Maxime Ripard
> > wrote:
> > > On Mon, Jul 17, 2017 at 02:57:19PM +0800, Chen-Yu Tsai wrote:
> > >> On Mon, Jul 17, 2
On 07/19/2017 06:02 PM, Rob Herring wrote:
diff --git a/drivers/media/v4l2-core/v4l2-async.c
b/drivers/media/v4l2-core/v4l2-async.c
index 851f128eba22..0a385d1ff28c 100644
--- a/drivers/media/v4l2-core/v4l2-async.c
+++ b/drivers/media/v4l2-core/v4l2-async.c
@@ -47,9 +47,7 @@ static bool match_fw
Hi Daniel,
On Tue, Jul 18, 2017 at 09:35:03AM +0200, Daniel Vetter wrote:
> On Tue, Jul 18, 2017 at 9:07 AM, Maxime Ripard
> wrote:
> > On Mon, Jul 17, 2017 at 02:57:19PM +0800, Chen-Yu Tsai wrote:
> >> On Mon, Jul 17, 2017 at 2:55 PM, Maxime Ripard
> >> wrote:
> >> > On Fri, Jul 14, 2017 at 04:
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