On Mon, Sep 25, 2017 at 9:53 AM, Simon Horman
wrote:
> Renesas ARM Based SoC Drivers Updates for v4.15
>
> Add basic support for R-Car V3M (R8A77970) SoC.
>
> Sergei Shtylyov says:
>
> * Add support for R-Car V3M (R8A77970) SoC power areas to the R-Car SYSC
> driver
On 10/20/2017 01:14 AM, Geert Uytterhoeven wrote:
> From: Sergei Shtylyov
>
> The PHY devices sometimes do have their reset signal (maybe even power
> supply?) tied to some GPIO and sometimes it also does happen that a boot
> loader does not leave it
On 10/20/2017 01:14 AM, Geert Uytterhoeven wrote:
> From: Sergei Shtylyov
>
> With the phylib now being aware of the "reset-gpios" PHY node property,
> there should be no need to frob the PHY reset in this driver anymore...
>
> Signed-off-by: Sergei Shtylyov
On Wed, Oct 11, 2017 at 03:50:13PM +0200, Geert Uytterhoeven wrote:
> Correct the USB subnodes in the example, cfr. commit f7d569c1e6a6fa73
> ("ARM: dts: r8a779x: Fix PCI bus dtc warnings"):
> 1. Drop the bogus 'device_type = "pci"' properties,
> 2. Correct the unit addresses.
>
> Update
On Thu, Oct 19, 2017 at 11:48:02AM +0800, Jeffy Chen wrote:
>
> Make edp display works on chromebook kevin(at least for boot animation).
>
> Also solve some issues i meet during the bringup.
>
> Changes in v6:
> Don't change order of rockchip_drm_psr_register().
>
> Changes in v5:
> Call the
On Fri, Oct 20, 2017 at 1:25 PM, Geert Uytterhoeven
wrote:
> Hi Linus,
>
> The following changes since commit 5ec8a41a36715cf543cb7c109097fb3b4cdfb427:
>
> pinctrl: sh-pfc: r8a7795: Add USB3.0 host support (2017-10-02 13:23:44
> +0200)
>
> are available in the
Hi Geert,
On 2017-10-20 09:15:50 +0200, Geert Uytterhoeven wrote:
> Hi Niklas,
>
> On Fri, Oct 20, 2017 at 1:32 AM, Niklas Söderlund
> wrote:
> > Commit 9cab88726929605 ("net: ethtool: Add back transceiver type")
> > restores the transceiver type to struct
Hi Linus,
The following changes since commit 5ec8a41a36715cf543cb7c109097fb3b4cdfb427:
pinctrl: sh-pfc: r8a7795: Add USB3.0 host support (2017-10-02 13:23:44 +0200)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
Hi Mike, Stephen,
The following changes since commit b4021bbe10017d994e5a96ebfd2677bbaf2b37e0:
clk: renesas: rcar-gen2: Delete error message for failed memory allocation
(2017-09-28 17:57:34 +0200)
are available in the git repository at:
Hello!
On 10/20/2017 11:14 AM, Geert Uytterhoeven wrote:
From: Sergei Shtylyov
The PHY devices sometimes do have their reset signal (maybe even power
supply?) tied to some GPIO and sometimes it also does happen that a boot
loader does not leave it
From: Fabrizio Castro
Add node for xhci. Boards DT files will enable it if needed.
Signed-off-by: Fabrizio Castro
Reviewed-by: Yoshihiro Shimoda
Signed-off-by: Simon Horman
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7791 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7790 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7792 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback
From: Biju Das
This patch adds DMA properties to the HSUSB node.
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Geert Uytterhoeven
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven
From: Geert Uytterhoeven
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven
From: Geert Uytterhoeven
Improve hardware description by adding clocks properties to the device
nodes corresponding to the CA9 CPU cores.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Dietmar Eggemann
The following 'capacity-dmips-mhz' dt property values are used:
Cortex-A15: 1024, Cortex-A7: 539
They have been derived form the cpu_efficiency values:
Cortex-A15: 3891, Cortex-A7: 2048
by scaling them so that the Cortex-A15s (big cores) use
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7794 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback
From: Geert Uytterhoeven
Currently only the primary CPU in the CA7 cluster has a clocks property,
while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven
From: Geert Uytterhoeven
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven
From: Geert Uytterhoeven
Add the missing definitions for the I (CPU) and G (Image Processing)
clocks, so these clocks can be referred to from device nodes in DT.
Note that these clocks are already fully supported otherwise (DT
bindings, Linux driver, r7s72100.dtsi),
From: Geert Uytterhoeven
Currently only the CPU cores in the CA15 cluster have clocks properties.
Add the missing clocks properties for the CPU cores in the CA7 cluster
to fix this.
Signed-off-by: Geert Uytterhoeven
Tested-by: Simon Horman
From: Geert Uytterhoeven
Improve hardware description by adding a clock property to the device
node corresponding to the CA9 CPU core.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Biju Das
Describe the PCI USB devices that are behind the PCI bridges, adding
necessary links to the USB PHY device.
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7793 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback
From: Jacopo Mondi
Add pin configuration subnode for ETHER pin group.
Signed-off-by: Jacopo Mondi
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Biju Das
Add device nodes for the r8a7745 internal PCI bridge devices.
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon
From: Jacopo Mondi
Enable ostm0 and ostm1 timers to be used as clock source and clockevent
source. The timers provides greater accuracy than the already enabled
mtu2 one.
With these enabled:
clocksource: ostm: mask: 0x max_cycles: 0x, max_idle_ns:
Use newly added R-Car GPIO Gen1 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in DT of r8a7778 SoC.
As the driver does not match on "renesas,gpio-r8a7778" there
are some run-time considerations for this patch:
* When a resulting DTB
From: Geert Uytterhoeven
Improve hardware description by adding clocks properties to the device
nodes corresponding to the CA9 CPU cores.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Geert Uytterhoeven
Improve hardware description by adding a clocks property to the device
node corresponding to the primary CA15 CPU core, which is for now the
only one described.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon
From: Biju Das
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Biju Das
Define the R8A7743 generic part of the HS-USB device node. It is up to the
board file to enable the device.
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
From: Geert Uytterhoeven
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU cores are driven by the same clock.
Add the missing clocks properties to fix this.
Signed-off-by: Geert Uytterhoeven
From: Biju Das
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers
attached to them.
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
From: Geert Uytterhoeven
Improve hardware description by adding a clock property to the device
node corresponding to the CA9 CPU core.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
Use newly added R-Car GPIO Gen1 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in DT of r8a7779 SoC.
As the driver does not match on "renesas,gpio-r8a7779" there
are some run-time considerations for this patch:
* When a resulting DTB
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7743 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback
From: Biju Das
Enable HS-USB device for the iWave G20D-Q7 carrier board based on
RZ/G1M.
Also disable the host mode support on usb otg port by default to avoid
pin conflicts.
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
From: Biju Das
Define the r8a7745 generic part of the USB PHY device node.
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Biju Das
Signed-off-by: Biju Das
Signed-off-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Geert Uytterhoeven
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven
From: Yoshihiro Shimoda
Since Salvator-X[S] have a USB2.0 dual-role channel (CN9), this patch
adds dr_mode property for USB2.0 channel 0 (EHCI/OHCI and HS-USB)
as "otg".
Signed-off-by: Yoshihiro Shimoda
Signed-off-by: Simon
From: Jacopo Mondi
Fix 'leds' node name indent as it was wrongly aligned.
Signed-off-by: Jacopo Mondi
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r7s72100-gr-peach.dts | 2 +-
1 file changed, 1
From: Geert Uytterhoeven
Use the preferred generic node name instead of the specific name.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7790.dtsi | 8
1 file
Use newly added R-Car GPIO Gen3 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7795 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback
From: Geert Uytterhoeven
Use the preferred generic node name instead of the specific name.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7794.dtsi | 4 ++--
1 file changed,
From: Geert Uytterhoeven
Use the preferred generic node name instead of the specific name.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7792.dtsi | 6 +++---
1 file
From: Fabrizio Castro
This patch adds a .dtsi that describes the camera daughter board
and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's
RZ/G1M/G1N Qseven carrier board, and the camera daughter board.
The camera daughter board .dtsi adds support
From: Geert Uytterhoeven
Use the preferred generic node name instead of the specific name.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
arch/arm/boot/dts/r8a7791.dtsi | 6 +++---
1 file
From: Vladimir Barinov
This adds gpio hogs for USB3 hub on ULCB Kingfisher board to power up and
remove from reset the hub
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
From: Vladimir Barinov
This supports PCA9548 I2C switch on I2C2 bus on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Kuninori Morimoto
"audio_clkout" is dummy clock of <_sound 0> to avoid clock loop
which invites probe conflict. Thus <_sound 0> and "audio_clkout"
should be same value.
On commit 5e2feac33095 ("arm64: renesas: salvator-common: sound
clock-frequency needs
From: Jacopo Mondi
MTU2 multi-function/multi-channel timer/counter is not enabled for
GR-Peach board. The timer is used as clock event source to schedule
wake-ups, and without this enabled all sleeps not performed through busy
waiting hang the board.
Signed-off-by:
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these second round of Renesas ARM based SoC DT updates for
v4.15.
This pull request is based on the previous round of
such requests, tagged as renesas-dt-for-v4.15,
which you have already pulled.
The following changes since commit
From: Yoshihiro Shimoda
Since a R-Car Gen3 bootloader enables the PFC of USB3.0 channel 0,
the USB3.0 host controller works without this setting on the kernel.
But, this setting should have salvator-common.dtsi. So, this patch
adds the pfc node for USB3.0
From: Vladimir Barinov
This supports TCA9539 gpio expanders on I2C2 bus on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Geert Uytterhoeven
Add a device node for the Interrupt Controller for External Devices
(INTC-EX) on R-Car D3, which serves external IRQ pins IRQ[0-5].
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Yoshihiro Shimoda
This patch adds PWM device nodes for r8a77995.
Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
Use newly added R-Car GPIO Gen3 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7796 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback
From: Geert Uytterhoeven
Add a device node for the Interrupt Controller for External Devices
(INTC-EX) on R-Car V3M, which serves external IRQ pins IRQ[0-5].
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Kuninori Morimoto
"audio_clkout" is dummy clock of <_sound 0> to avoid clock loop
which invites probe conflict. Thus <_sound 0> and "audio_clkout"
should be same value.
On commit 2752660a37ae ("arm64: dts: renesas: ulcb: sound
clock-frequency needs
From: Vladimir Barinov
This supports USB3.0 Host on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Vladimir Barinov
This supports TCA9539 gpio expanders on I2C4 bus on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Geert Uytterhoeven
Add a device node for the Interrupt Controller for External Devices
(INTC-EX) on R-Car M3-W, which serves external IRQ pins IRQ[0-5].
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Vladimir Barinov
This supports PCA9548 I2C switch on I2C4 bus on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Sergei Shtylyov
Define the Eagle board dependent part of the EtherAVB device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov
From: Vladimir Barinov
This supports USB2.0 Host channel 0 on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
From: Vladimir Barinov
This supports SCIF1 on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Vladimir Barinov
Add the initial device tree for the H3ULCB ES1.x SoC with Kingfisher
extension infotainment board.
Signed-off-by: Vladimir Barinov
Signed-off-by: Simon Horman
---
From: Sergei Shtylyov
Add the initial device tree for the R8A77970 SoC based Eagle board.
The board has 1 debug serial port (SCIF0); include support for it,
so that the serial console can work.
Based on the original (and large) patch by Vladimir Barinov
From: Vladimir Barinov
This supports PCIE0/1 on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Vladimir Barinov
This supports CAN0/1 on ULCB Kingfisher board
Signed-off-by: Vladimir Barinov
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
From: Yoshihiro Shimoda
This patch enables PWM channel 0 and 1 on the draak. Each channel
connects to LTC2644 for brightness control.
Signed-off-by: Yoshihiro Shimoda
Reviewed-by: Geert Uytterhoeven
From: Vladimir Barinov
Add the initial device tree for the H3ULCB ES2.0+ SoC with Kingfisher
extension infotainment board.
Signed-off-by: Vladimir Barinov
Signed-off-by: Simon Horman
---
From: Yoshihiro Shimoda
Since the Ethernet AVB driver doesn't support AVB_PHY_INT handling
and it will be handled by a phy driver as a gpio pin, this patch
removes the "avb_phy_int" from the avb_pins node.
Reported-by: Geert Uytterhoeven
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these second round of Renesas ARM64 based SoC DT updates for
v4.15.
This pull request is based on the previous round of
such requests, tagged as renesas-arm64-dt-for-v4.15,
which I you have already pulled.
The following changes since commit
From: Yoshihiro Shimoda
Since the Ethernet AVB driver doesn't support AVB_PHY_INT handling
and it will be handled by a phy driver as a gpio pin, this patch
removes the "avb_phy_int" from the avb_pins node.
Reported-by: Geert Uytterhoeven
From: Yoshihiro Shimoda
Since the Ethernet AVB driver doesn't support AVB_PHY_INT handling
and it will be handled by a phy driver as a gpio pin, this patch
removes the "avb_phy_int" from the avb_pins node.
Reported-by: Sergei Shtylyov
On 20 October 2017 at 05:12, Yoshihiro Shimoda
wrote:
> This patch set is based on mainline v4.14-rc5.
>
> Changes from v1:
> - Calculate the max size of swiotlb memory instead of hardcoded value
>in patch 1.
> - Add Reviewed-by from Geert-san in patch 2.
On 16 October 2017 at 09:46, Simon Horman wrote:
> On Sun, Oct 15, 2017 at 02:46:15PM +0200, Wolfram Sang wrote:
>> These boards are known to have eMMC issues with the default driver type.
>> Specify a working one.
>>
>> Signed-off-by: Wolfram Sang
On 18 October 2017 at 09:00, Simon Horman wrote:
> Add fallback compatibility strings for R-Car Gen 1, 2 and 3 to the SDHI
> bindings and driver.
>
> In the case of Renesas R-Car hardware we know that there are generations of
> SoCs, f.e. Gen 1 and 2. But beyond that
On 14 October 2017 at 21:17, Wolfram Sang
wrote:
> Fix the drivers and add some docs according to the outcome of this discussion
> [1] we had recently. The motivation from the patch description:
>
> Bail out everytime when mmc_regulator_get_supply() returns an
On 15 October 2017 at 14:46, Wolfram Sang
wrote:
> Parse the new binding and store it in the host struct after doing some
> sanity checks. The code is designed to support fixed SD driver type if
> we ever need that.
>
> Signed-off-by: Wolfram Sang
On 15 October 2017 at 14:46, Wolfram Sang
wrote:
> Some boards may have to use a certain driver type (or drive strength) to
> achieve stable eMMC communication. Describe a binding to set this up via
> DT.
>
> Signed-off-by: Wolfram Sang
Hi Simon,
On Fri, Oct 20, 2017 at 11:27 AM, Simon Horman wrote:
> On Mon, Oct 16, 2017 at 11:08:45AM +0200, Geert Uytterhoeven wrote:
>> Add a defconfig for Renesas R-Car Gen3 boards.
>>
>> Signed-off-by: Geert Uytterhoeven
>> ---
>> Against
Please include some changelog text here, preferably motivating the change.
On Fri, Oct 13, 2017 at 05:06:33PM +0100, Fabrizio Castro wrote:
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Chris Paterson
On Mon, Oct 16, 2017 at 10:36 AM, Geert Uytterhoeven
wrote:
> During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their
> clock register state is lost. Note that as the boot loader skips most
> initialization after resume, clock register state differs from
On Fri, Oct 20, 2017 at 11:06:56AM +0200, Arnd Bergmann wrote:
> On Fri, Oct 20, 2017 at 11:03 AM, Simon Horman wrote:
> > On Thu, Oct 19, 2017 at 11:39:45PM +0200, Arnd Bergmann wrote:
> >> On Fri, Sep 29, 2017 at 1:52 PM, Simon Horman
>
> >> That one last commit doesn't
On Mon, Oct 16, 2017 at 11:08:45AM +0200, Geert Uytterhoeven wrote:
> Add a defconfig for Renesas R-Car Gen3 boards.
>
> Signed-off-by: Geert Uytterhoeven
> ---
> Against renesas-devel-20171013-v4.14-rc4.
> Not intended for upstream merge.
>
> Loosely based on arm64
On Tue, Oct 17, 2017 at 08:09:48AM +0200, Simon Horman wrote:
> Use recently posted R-Car SDHI Gen 1, 2 and 3 fallback compat strings
> in the DT of Renesas ARM and arm64 based SoCs.
>
> Based on renesas-devel-20171016-v4.14-rc5
>
> Has a binding documentation but no run-time dependency on
>
On Wed, Oct 18, 2017 at 10:33:46AM +0100, Biju Das wrote:
> From: Fabrizio Castro
Please include some text, preferably motivating this change,
here.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
On Wed, Oct 18, 2017 at 09:27:21AM +0200, Simon Horman wrote:
> Use recently posted R-Car Gen 1 and 2 Ether fallback compat strings
> in the DT of Renesas ARM based SoCs.
>
> Based on renesas-devel-20171018-v4.14-rc5
>
> Has a binding documentation but no run-time dependency on
> "[PATCH
On Fri, Oct 20, 2017 at 10:14:17AM +0200, Geert Uytterhoeven wrote:
> Hi David, Andrew, Florian, Simon, Magnus,
>
> This patch series adds optional PHY reset support to phylib.
>
> The first two patches are destined for David's net-next tree. They add
> core PHY reset code, and update a
On Thu, Oct 19, 2017 at 11:39:45PM +0200, Arnd Bergmann wrote:
> On Fri, Sep 29, 2017 at 1:52 PM, Simon Horman
> wrote:
> >
> > Renesas ARM64 Based SoC DT Updates for v4.15
> >
> > * r8a7795 (H3)
> > -
From: Sergei Shtylyov
With the phylib now being aware of the "reset-gpios" PHY node property,
there should be no need to frob the PHY reset in this driver anymore...
Signed-off-by: Sergei Shtylyov
Acked-by: Nicolas Ferre
Describe the GPIO used to reset the Ethernet PHY for EthernetAVB.
This allows the driver to reset the PHY during probe and after system
resume.
This fixes Ethernet operation after resume from s2ram on Salvator-XS,
where the enable pin of the regulator providing PHY power is connected
to PRESETn,
Describe the GPIO used to reset the Ethernet PHY for EthernetAVB.
This allows the driver to reset the PHY during probe and after system
resume.
On ULCB, the enable pin of the regulator providing PHY power is always
pulled high, but the driver may still need to reset the PHY if this
wasn't done by
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