Hi Kieran,
On Wednesday, 4 April 2018 19:00:10 EEST Kieran Bingham wrote:
> Hi Laurent,
>
> Thank you for the patch.
>
> I don't envy you on having to deal with this one ... it's a bit of a pain
> ...
Yes it was a bit painful :-/ The devil was both in the big picture and the
details this
Hi Kieran,
On Wednesday, 4 April 2018 19:16:46 EEST Kieran Bingham wrote:
> On 26/02/18 21:45, Laurent Pinchart wrote:
> > Display list completion is already reported to the frame end handler,
> > but that mechanism is global to all display lists. In order to implement
> > BRU and BRS
[re-sending due to lost To: field]
Hello Wolfram, Vladimir,
Thanks for your precious inputs.
I think you outlined two topics in your comments (based on the
description submitted with the patch). One (primary?) is related to
async probing and one (secondary, but still interesting) is related to
Hello Wolfram, Vladimir,
Thanks for your precious inputs.
I think you outlined two topics in your comments (based on the
description submitted with the patch). One (primary?) is related to
async probing and one (secondary, but still interesting) is related to
the minor (~7ms -> ~1ms) startup
Hi Kieran,
On Wednesday, 4 April 2018 19:15:19 EEST Kieran Bingham wrote:
> On 02/04/18 13:35, Laurent Pinchart wrote:
>
>
>
> >>> +/* Setup the output side of the pipeline (WPF and LIF). */
> >>> +static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
> >>> +
This PHY is still mostly undocumented -- the only documented registers
exist on R-Car V3H (R8A77980) SoC where this PHY stays in a powered-down
state after a reset and thus we must power it on for PCIe to work...
Signed-off-by: Sergei Shtylyov
---
The patch
From: Wolfram Sang
If we detect an incompatible scatterlist, we should fall back to PIO,
too.
Signed-off-by: Wolfram Sang
---
I found this while working on the RX DMA issue. I don't see a reason why we
shouldn't fall back in
From: Wolfram Sang
Early revisions of certain SoCs cannot do multiple DMA RX streams in
parallel. To avoid data corruption, only allow one DMA RX channel and
fall back to PIO, if needed.
Signed-off-by: Wolfram Sang
---
Okay,
Hi Laurent,
And so - the final patch (of the series)
On 26/02/18 21:45, Laurent Pinchart wrote:
> Some VSP instances have two blending units named BRU (Blend/ROP Unit)
> and BRS (Blend/ROP Sub unit). The BRS is a smaller version of the BRU
> with only two inputs, but otherwise offers similar
Hi Laurent,
On 26/02/18 21:45, Laurent Pinchart wrote:
> Dynamic assignment of the BRU and BRS to pipelines is prone to
> regressions, add messages to make debugging easier. Keep it as a
> separate commit to ease removal of those messages once the code will
> deem to be completely stable.
>
>
Hi Laurent,
On 26/02/18 21:45, Laurent Pinchart wrote:
> Display list completion is already reported to the frame end handler,
> but that mechanism is global to all display lists. In order to implement
> BRU and BRS reassignment in DRM pipelines we will need to wait for
> completion of a
Hi Laurent,
On 02/04/18 13:35, Laurent Pinchart wrote:
>>> +/* Setup the output side of the pipeline (WPF and LIF). */
>>> +static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
>>> +struct vsp1_pipeline *pipe)
>>> +{
>>> + struct
Hi Laurent,
Thank you for the patch.
I don't envy you on having to deal with this one ... it's a bit of a pain ...
On 26/02/18 21:45, Laurent Pinchart wrote:
> The VSPDL variant drives two DU channels through two LIF and two
> blenders, BRU and BRS. The DU channels thus share the five available
HSCIF has facilities that allow moving the RX sampling point by between
-8 and 7 sampling cycles (one sampling cycles equals 1/15 of a bit
by default) to improve the error margin in case of slightly mismatched
bit rates between sender and receiver.
This patch tries to determine if shifting the
Hi Laurent,
On 26/02/18 21:45, Laurent Pinchart wrote:
> The DRM support code manages a pipeline of VSP entities, each backed by
> a media entity. When starting or stopping the pipeline, it starts and
> stops the media pipeline through the media API in order to store the
> pipeline pointer in
Document PFC support for the R8A77470 SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
V1->V2:
* Incorporated sergie's review comment.
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
1 file changed,
Hi,
This patch series aims to add support for r8a77470 PFC driver
This patch is tested against "sh-pfc" branch of 'renesas-drivers.git'
repo.
V1-->V2
Incorporated sergie's review comment.
Biju Das (2):
pinctrl: sh-pfc: Add r8a77470 PFC support
dt-bindings: pinctrl: sh-pfc:
Add PFC support for the R8A77470 SoC including pin groups for
some on-chip devices such as SCIF, AVB and MMC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
V1->V2:
* No change
drivers/pinctrl/sh-pfc/Kconfig|5 +
Hi Maxime,
On Thursday, 29 March 2018 14:30:39 EEST Maxime Ripard wrote:
> On Tue, Feb 13, 2018 at 12:01:32AM +0100, Niklas Söderlund wrote:
> > + switch (priv->lanes) {
> > + case 1:
> > + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_0;
> > + break;
> > + case 2:
> > +
Hello,
On Wednesday, 14 March 2018 00:23:49 EEST Kieran Bingham wrote:
> Hi Niklas
>
> Thank you for this patch ...
> I know it has been a lot of work getting this and the VIN together!
>
> On 13/02/18 00:01, Niklas Söderlund wrote:
> > A V4L2 driver for Renesas R-Car MIPI CSI-2 receiver. The
Hi Niklas,
Thank you for the patch.
On Tuesday, 13 February 2018 01:01:32 EEST Niklas Söderlund wrote:
> A V4L2 driver for Renesas R-Car MIPI CSI-2 receiver. The driver
> supports the R-Car Gen3 SoCs where separate CSI-2 hardware blocks are
> connected between the video sources and the video
Hi,
Thanks for the feedback.
> -Original Message-
> From: Sergei Shtylyov [mailto:sergei.shtyl...@cogentembedded.com]
> Sent: 04 April 2018 15:44
> To: Biju Das ; Linus Walleij
> ; Rob Herring ; Mark Rutland
>
Hi Niklas,
Thank you for the patch.
On Tuesday, 13 February 2018 01:01:31 EEST Niklas Söderlund wrote:
> Documentation for Renesas R-Car MIPI CSI-2 receiver. The CSI-2 receivers
> are located between the video sources (CSI-2 transmitters) and the video
> grabbers (VIN) on Gen3 of Renesas R-Car
Calling 2 patches the same way was a bad idea...
Document PFC support for the R8A77470 SoC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi,
This patch series aims to add support for r8a77470 PFC driver
This patch is tested against "sh-pfc" branch of 'renesas-drivers.git'
repo.
Biju Das (2):
pinctrl: sh-pfc: Add r8a77470 PFC support
pinctrl: sh-pfc: Add r8a77470 PFC support
.../bindings/pinctrl/renesas,pfc-pinctrl.txt
Add PFC support for the R8A77470 SoC including pin groups for
some on-chip devices such as SCIF, AVB and MMC.
Signed-off-by: Biju Das
Reviewed-by: Fabrizio Castro
---
drivers/pinctrl/sh-pfc/Kconfig|5 +
On 3 April 2018 at 23:57, Wolfram Sang wrote:
> From: Masaharu Hayakawa
>
> If an error was detected when CMD23 was issued, command sequence should
> be terminated with errors and CMD23 should be issued after retuning.
>
> Fixes: 8b22c3c18be5
Hi Niklas,
It might be a good idea if you can rebase the patch series on the latest
master (we've just synced to Linus' master tree) and incorporate the few
comments that Laurent had.
Then once the merge window closes I can make the pull request, probably on
the 16th.
Regards,
Hans
On
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