Hello,
On Tue, 17 Apr 2018 11:21:02 +0300
Sergei Shtylyov wrote:
> Hello!
>
> On 4/17/2018 12:50 AM, Mylène Josserand wrote:
>
> > To prepare the support for sun8i-a83t, rename the variable name
>
> s/variable/macro/ maybe? Also "rename the ... name" sounds tautological...
Thank you fo
Hello Ondrej,
On Tue, 17 Apr 2018 04:15:00 +0200
Ondřej Jirman wrote:
> Hello Mylène,
>
> Please also add this:
>
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index ce53ceaf4cc5..d9c8ecf88ec6 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/K
Hello Maxime,
On Tue, 17 Apr 2018 13:20:38 +0200
Maxime Ripard wrote:
> On Mon, Apr 16, 2018 at 11:50:30PM +0200, Mylène Josserand wrote:
> > @@ -535,8 +599,12 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
> > return !ret;
> > }
> >
> > -static bool sunxi_mc_smp_cpu_can_disable(
From: Niklas Söderlund
Based on previous work by Ryo Kataoka .
Signed-off-by: Niklas Söderlund
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 59 +++
1 file changed, 59 insertions(+)
Hi Simon,
This patch depends on '[PATCH 0/2] thermal: rcar_gen3_thermal: add
r8a77965 s
From: Niklas Söderlund
Signed-off-by: Niklas Söderlund
---
drivers/thermal/rcar_gen3_thermal.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 561a0a332208504a..c04182e1518cd613 100644
--- a/drivers/thermal/rca
From: Niklas Söderlund
Hi,
This series adds DT documentation and driver support to the
rcar-gen3-thermal driver for r8a77965.
Niklas Söderlund (2):
dt-bindings: thermal: rcar-gen3-thermal: add r8a77965
thermal: rcar_gen3_thermal: add r8a77965 support
.../devicetree/bindings/thermal/rcar-
From: Niklas Söderlund
Based on previous work by Ryo Kataoka .
Signed-off-by: Niklas Söderlund
---
.../devicetree/bindings/thermal/rcar-gen3-thermal.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.tx
From: Niklas Söderlund
Hi,
This series updates the constants used to convert the register values to
degrease. It is based on feedback from the hardware team communicated
through BSP patches and updated datasheets. :-)
Hien Dang (1):
thermal: rcar_gen3_thermal: Update calculation formula due
From: Niklas Söderlund
Change the upper limit to clamp the high temperature value to 120C when
setting trip points.
Signed-off-by: Niklas Söderlund
---
drivers/thermal/rcar_gen3_thermal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.
From: Hien Dang
Due to hardware evaluation result,
Max temperature is changed from 96 to 116 degree Celsius.
Also, calculation formula and pseudo FUSE values are changed accordingly.
Signed-off-by: Dien Pham
Signed-off-by: Hien Dang
Signed-off-by: Niklas Söderlund
---
drivers/thermal/rcar_ge
From: Niklas Söderlund
Hi Simon,
This series decrease the hysteresis from 2C to 1C for the two boards we
have described upstream. They have no dependencies and are ready to be
accepted if the review is in favor of them.
Niklas Söderlund (2):
arm64: dts: renesas: r8a7795: decrease temperatur
From: Niklas Söderlund
To incorporate more tests by the hardware team decrease the hysteresis
value to 1C.
Signed-off-by: Niklas Söderlund
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r
From: Niklas Söderlund
To incorporate more tests by the hardware team decrease the hysteresis
value to 1C.
Signed-off-by: Niklas Söderlund
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r
From: Niklas Söderlund
The datasheet have been expanded with more registers and the DT files
have been updated with the new size. This change updates the example so
writing new DT files can use the enchanted driver which uses the new
registers.
Signed-off-by: Niklas Söderlund
---
.../devicetre
On 04/17/2018 01:05 PM, Wolfram Sang wrote:
>> @@ -2302,6 +2305,7 @@ static int __maybe_unused ravb_resume(struct device
>> *dev)
>> {
>> struct net_device *ndev = dev_get_drvdata(dev);
>> struct ravb_private *priv = netdev_priv(ndev);
>> +struct platform_device *pdev = priv->pdev;
Hi Michel,
On Tue, Apr 17, 2018 at 1:04 PM, Michel Pollet
wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
>
> Signed-off-by: Michel Pollet
> ---
> Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/D
Hi Geert,
On Tue, Apr 17, 2018 at 04:30:03PM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> CC Christoph
>
> On Tue, Apr 17, 2018 at 4:13 PM, Jacopo Mondi
> wrote:
> > As of commit 205e1b7f51e4 ("dma-mapping: warn when there is no
> > coherent_dma_mask") the Migo-R platform devices registered
With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
operations observe dev->dma_pfn_offset") the generic DMA allocation
function on which the SH 'dma_alloc_coherent()' function relies on,
accesses the 'dma_pfn_offset' field of struct device.
Unfortunately the 'dma_generic_alloc_co
Hi Jacopo,
CC Christoph
On Tue, Apr 17, 2018 at 4:13 PM, Jacopo Mondi wrote:
> As of commit 205e1b7f51e4 ("dma-mapping: warn when there is no
> coherent_dma_mask") the Migo-R platform devices registered without a DMA
> mask and coherent DMA mask issue the following warning
>
> WARNING: CPU: 0 PI
Hi Geert,
On Tue, Apr 17, 2018 at 04:04:27PM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> Thanks for your patch!
>
> On Tue, Apr 17, 2018 at 3:35 PM, Jacopo Mondi
> wrote:
> > With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
> > operations observe dev->dma_pfn_offset") t
From: Simon Horman
Date: Tue, 17 Apr 2018 10:50:28 +0200
> From: Kazuya Mizuguchi
>
> This patch corrects writing 1 to reserved bits.
> The write value should be 0.
>
> Signed-off-by: Kazuya Mizuguchi
> Signed-off-by: Simon Horman
How are we ending up in situations where the driver is tryin
From: Simon Horman
Date: Tue, 17 Apr 2018 10:50:29 +0200
> From: Kazuya Mizuguchi
>
> Signed-off-by: Kazuya Mizuguchi
> Signed-off-by: Simon Horman
Why? What was wrong with it?
Need more text and explanations in these commit messages please.
From: Simon Horman
Date: Tue, 17 Apr 2018 10:50:26 +0200
> From: Masaru Nagai
>
> [ 58.490829] =
> [ 58.495205] [ INFO: inconsistent lock state ]
> [ 58.499583] 4.9.0-yocto-standard-7-g2ef7caf #57 Not tainted
...
> Fixes: f51bdc236b6c ("ravb: Add dma q
As of commit 205e1b7f51e4 ("dma-mapping: warn when there is no
coherent_dma_mask") the Migo-R platform devices registered without a DMA
mask and coherent DMA mask issue the following warning
WARNING: CPU: 0 PID: 1 at ./include/linux/dma-mapping.h:516 0x40159e20
Set dma mask and coherent DMA mask
Hi Jacopo,
Thanks for your patch!
On Tue, Apr 17, 2018 at 3:35 PM, Jacopo Mondi wrote:
> With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
> operations observe dev->dma_pfn_offset") the generic DMA allocation
> function on which the SH 'dma_alloc_coherent()' function relies on
Hi Thomas,
On Tue, Apr 17, 2018 at 03:54:07PM +0200, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 17 Apr 2018 15:35:23 +0200, Jacopo Mondi wrote:
> > With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
> > operations observe dev->dma_pfn_offset") the generic DMA allocation
> > fun
Hello,
On Tue, 17 Apr 2018 15:35:23 +0200, Jacopo Mondi wrote:
> With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
> operations observe dev->dma_pfn_offset") the generic DMA allocation
> function on which the SH 'dma_alloc_coherent()' function relies on,
> access the 'dma_pfn_of
With commit ce88313069c36eef80f21fd7 ("arch/sh: make the DMA mapping
operations observe dev->dma_pfn_offset") the generic DMA allocation
function on which the SH 'dma_alloc_coherent()' function relies on,
access the 'dma_pfn_offset' field of struct device.
Unfortunately the 'dma_generic_alloc_cohe
On Tue, Apr 17, 2018 at 12:04:18PM +0100, Michel Pollet wrote:
> This documents the RZ/N1 bindings for the RZN1D-DB board.
>
> Signed-off-by: Michel Pollet
> ---
> Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
Please add acks/revi
Hi Biju,
+ Sergei
On Tue, Apr 17, 2018 at 11:07 AM, Biju Das wrote:
>> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
>> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das wrote:
>> > Add PFC support for the R8A77470 SoC including pin groups for some
>> > on-chip devices such as SC
Hi Simon,
On Tue, Apr 17, 2018 at 10:50 AM, Simon Horman
wrote:
> From: Masaru Nagai
>
> [ 58.490829] =
> [ 58.495205] [ INFO: inconsistent lock state ]
> [ 58.499583] 4.9.0-yocto-standard-7-g2ef7caf #57 Not tainted
Can this be triggered on contemporary
On Tue, Apr 17, 2018 at 7:42 AM, Phil Edworthy
wrote:
> The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> per GPIO in port A, but the driver currently only supports 1 interrupt.
> See the DesignWare DW_apb_gpio Databook description of the
> 'GPIO_INTR_IO' parameter.
>
> This c
I have pushed renesas-drivers-2018-04-17-v4.17-rc1 to
https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git
This tree is meant to ease development of platform support and drivers
for Renesas ARM SoCs. It is created by merging (a) the for-next branches
of various subsystem trees an
Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.
Add a special enable method for second CA8 of the Renesas RZ/N1D
(R9A06G032).
Signed-off-by: Michel Pollet
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentat
The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started.
Signed-off-by: Michel Pollet
---
arch/arm/mach-shmobile/Makefile| 1 +
arch/arm/mach-shmobile/smp-r9a06g032.c | 85 ++
2 files change
*WARNING -- this requires the base RZ/N1 base patches (v5) already posted
This patch series is for enabling the second CA7 of the RZ/N1D.
It's based on a spin_table method, and it reuses the same binding
property as that driver.
v2:
+ Added suggestions from Florian Fainelli
+ Use __pa_symbol(
The DesignWare GPIO IP can be configured for either 1 interrupt or 1
per GPIO in port A, but the driver currently only supports 1 interrupt.
See the DesignWare DW_apb_gpio Databook description of the
'GPIO_INTR_IO' parameter.
This change allows the driver to work with up to 32 interrupts, it will
Hi Rob,
On 16 April 2018 21:03 Rob Herring wrote:
> On Fri, Apr 13, 2018 at 09:51:12AM +0100, Phil Edworthy wrote:
> > The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> > per GPIO in port A, but the driver currently only supports 1 interrupt.
> > See the DesignWare DW_apb_gpio
On Tue, Apr 17, 2018 at 7:17 PM, Maxime Ripard
wrote:
> On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
>> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
>> wrote:
>> > Move the assembly code for cluster cache enabling and resuming
>> > into an assembly file instead of having it
On Mon, Apr 16, 2018 at 11:50:30PM +0200, Mylène Josserand wrote:
> @@ -535,8 +599,12 @@ static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
> return !ret;
> }
>
> -static bool sunxi_mc_smp_cpu_can_disable(unsigned int __unused)
> +static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu
On Tue, Apr 17, 2018 at 03:57:07PM +0800, Chen-Yu Tsai wrote:
> >> @@ -697,6 +700,8 @@ static int __init sunxi_mc_smp_init(void)
> >> break;
> >> }
> >>
> >> + is_sun8i = sunxi_mc_smp_data[i].is_sun8i;
> >> +
> >
> > Do we really need to cache it? Can't we just have
On Tue, Apr 17, 2018 at 11:12:41AM +0800, Chen-Yu Tsai wrote:
> On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
> wrote:
> > Move the assembly code for cluster cache enabling and resuming
> > into an assembly file instead of having it directly in C code.
> >
> > Remove the CFLAGS because we are
on the previous versions!
v5:
+ Given the problems I have with getting in some structure around the
sysctrl block, I've removed the MFD, I've now attached a simple reboot
driver on it's own pair of registers.
+ Rebased on next-20180417
v4:
+ Fixes for suggestions by Simon Horm
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/r9a06g03
Add the RZ/N1D SoC to the reset of the Renesas SoC Collection.
Signed-off-by: Michel Pollet
---
arch/arm/mach-shmobile/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 96672da..fcc273f 100644
--- a/arch/arm/mach
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
as part of the sysctrl MFD to handle rebooting the CA7 cores.
This documents the driver bindings.
Signed-off-by: Michel Pollet
---
.../devicetree/bindings/power/renesas,rzn1-reboot.txt | 17 +
1 file changed, 17 inser
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032-rz
The Renesas RZ/N1 Family (Part #R9A06G0xx) needs a small driver
to reboot the Cortex-A7 cores. This driver is a sub driver of
the sysctrl MFD.
Signed-off-by: Michel Pollet
---
drivers/power/reset/Kconfig | 7 +++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/rzn1-reboot.c
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt
b/Documentation/devicetree/bin
Hi Mylène,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on arm-soc/for-next]
[also build test ERROR on v4.17-rc1 next-20180417]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
On Tue, Apr 17, 2018 at 10:50:29AM +0200, Simon Horman wrote:
> From: Kazuya Mizuguchi
>
> Signed-off-by: Kazuya Mizuguchi
> Signed-off-by: Simon Horman
> ---
> drivers/net/ethernet/renesas/ravb.h | 5 -
> drivers/net/ethernet/renesas/ravb_main.c | 15 ---
> 2 files chang
On Tue, Apr 17, 2018 at 10:50:26AM +0200, Simon Horman wrote:
> From: Masaru Nagai
>
> [ 58.490829] =
> [ 58.495205] [ INFO: inconsistent lock state ]
> [ 58.499583] 4.9.0-yocto-standard-7-g2ef7caf #57 Not tainted
> [ 58.505529]
> @@ -2302,6 +2305,7 @@ static int __maybe_unused ravb_resume(struct device
> *dev)
> {
> struct net_device *ndev = dev_get_drvdata(dev);
> struct ravb_private *priv = netdev_priv(ndev);
> + struct platform_device *pdev = priv->pdev;
Minor nit: I'd save this line...
> + if
Hi Florian,
On 16 April 2018 22:46, Florian Fainelli:
> Hi Michel,
>
> On 04/16/2018 02:34 AM, Michel Pollet wrote:
> > The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
> > requires a special enable method to get it started at boot time.
> >
> > Signed-off-by: Michel Pollet
>
Hi Geert,
Thanks for the comment.
> Subject: Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support
> Hi Biju,
>
> On Wed, Apr 4, 2018 at 5:22 PM, Biju Das wrote:
> > Add PFC support for the R8A77470 SoC including pin groups for some
> > on-chip devices such as SCIF, AVB and MMC.
> >
> >
From: Kazuya Mizuguchi
This patch corrects writing 1 to reserved bits.
The write value should be 0.
Signed-off-by: Kazuya Mizuguchi
Signed-off-by: Simon Horman
---
drivers/net/ethernet/renesas/ravb.h | 12
drivers/net/ethernet/renesas/ravb_main.c | 9 +
drivers/net/
From: Kazuya Mizuguchi
This patch sets from two descriptor to one descriptor because R-Car Gen3
does not have the 4 bytes alignment restriction of the transmission buffer.
Signed-off-by: Kazuya Mizuguchi
Signed-off-by: Simon Horman
---
drivers/net/ethernet/renesas/ravb.h | 6 +-
driver
From: Kazuya Mizuguchi
Signed-off-by: Kazuya Mizuguchi
Signed-off-by: Simon Horman
---
drivers/net/ethernet/renesas/ravb.h | 5 -
drivers/net/ethernet/renesas/ravb_main.c | 15 ---
2 files changed, 20 deletions(-)
diff --git a/drivers/net/ethernet/renesas/ravb.h
b/drive
From: Kazuya Mizuguchi
This patch fixes the problem that ptp4l command does not work after
suspend and resume.
Add the initial setting in ravb_suspend() and ravb_resume(),
because ptp does not work.
Fixes: a0d2f20650e8 ("Renesas Ethernet AVB PTP clock driver")
Signed-off-by: Kazuya Mizuguchi
Si
From: Masaru Nagai
[ 58.490829] =
[ 58.495205] [ INFO: inconsistent lock state ]
[ 58.499583] 4.9.0-yocto-standard-7-g2ef7caf #57 Not tainted
[ 58.505529] -
[ 58.509904] inconsistent {HARDIRQ-ON-W} -> {IN-HARDIRQ-W} usa
Hi Sergei,
this series is composed of otherwise unrelated RAVB patches from the R-Car
BSP v3.6.2 which at a first pass seem worth considering for upstream.
I would value your feedback on these patches so they can either proceed
into net-next or remain local to the BSP.
Thanks!
Kazuya Mizuguchi
Hi Michel,
On Tue, Apr 17, 2018 at 9:56 AM, Michel Pollet
wrote:
> On 13 April 2018 19:06, Rob Herring:
>> On Tue, Apr 10, 2018 at 09:30:03AM +0100, Michel Pollet wrote:
>> > The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function system
>> > controller. This documents the node used to en
Hello!
On 4/17/2018 12:50 AM, Mylène Josserand wrote:
To prepare the support for sun8i-a83t, rename the variable name
s/variable/macro/ maybe? Also "rename the ... name" sounds tautological...
that handles the power-off of clusters because it is different from
sun9i-a80 to sun8i-a83t.
T
On Tue, Apr 17, 2018 at 3:52 PM, Maxime Ripard
wrote:
> Hi,
>
> On Mon, Apr 16, 2018 at 11:50:29PM +0200, Mylène Josserand wrote:
>> To prepare the support of sun8i-a83t, add a field in the smp_data
>> structure to know if we are on sun9i-a80 or sun8i-a83t.
>>
>> Add also a global variable to retr
Hi Rob,
On 13 April 2018 19:06, Rob Herring:
> On Tue, Apr 10, 2018 at 09:30:03AM +0100, Michel Pollet wrote:
> > The Renesas RZ/N1 Family (Part #R9A06G0xx) has a multi-function system
> > controller. This documents the node used to encapsulate it's sub
> > drivers.
> >
> > Signed-off-by: Michel P
Hi,
On Mon, Apr 16, 2018 at 11:50:29PM +0200, Mylène Josserand wrote:
> To prepare the support of sun8i-a83t, add a field in the smp_data
> structure to know if we are on sun9i-a80 or sun8i-a83t.
>
> Add also a global variable to retrieve which architecture we are
> having.
>
> Signed-off-by: My
Hi Sergei,
On Mon, Apr 16, 2018 at 5:06 PM, Sergei Shtylyov
wrote:
> On 04/16/2018 04:02 PM, Geert Uytterhoeven wrote:
>>> Add the pin I/O voltage level control to the R8A77980 PFC driver.
>>
>> Subject says r8a77970?
>
>Typo, I guess. :-)
>
>>> Loosely based on the original (and large) patch
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