[PATCH 3/4] serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE

There is no more need for SCIx_RZ_SCIFA_REGTYPE now that SCIx_SH4_SCIF_REGTYPE can provide the same register/address definitions. Also, R7S9210 no longer needs a special compatible since the standard "renesas,scif" will work just fine. Signed-off-by: Chris Brandt ---

[PATCH 4/4] serial: sh-sci: Improve support for separate TEI and DRI interrupts

Some SCIF versions mux error and break interrupts together and then provide a separate interrupt ID for just TEI/DRI. Allow all 6 types of interrupts to be specified via platform data (or DT) and for any signals that are muxed together (have the same interrupt number) simply register one handler.

[PATCH 1/4] serial: sh-sci: Improve interrupts description

Describe interrupts property in more detail, especially when there are more than one interrupt. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- .../devicetree/bindings/serial/renesas,sci-serial.txt| 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff

[PATCH 0/4] serial: sh-sci: Clean up previous RZ/A2 support

This patch series doesn't really provide much new functionality, but rather provides a cleaner solution for adding RZ/A2 support. Chris Brandt (4): serial: sh-sci: Improve interrupts description serial: sh-sci: Allow for compressed SCIF address serial: sh-sci: Remove SCIx_RZ_SCIFA_REGTYPE

[PATCH 2/4] serial: sh-sci: Allow for compressed SCIF address

Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers. Use the register area size to determine the spacing between register. Signed-off-by: Chris Brandt --- drivers/tty/serial/sh-sci.c | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git

[PATCH v3 2/2] dt-bindings: arm: Document RZ/A2 SoC DT bindings

Add device tree bindings documentation for Renesas RZ/A2 (r7s9210) SoC. Also document new option for "renesas,bsid" Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven --- v3: * added "or Boundary Scan ID Register" to description v2: * added Reviewed-by * added renesas,bsid comment

[PATCH v3 1/2] soc: renesas: identify RZ/A2

Add support for identifying the RZ/A2M (R7S9210) SoC. Also add support for reading the BSID register which is a different format than the PRR. Signed-off-by: Chris Brandt --- v2: * Remove 'hard coded' section because there will not be andy non-DT legacy support needed * Make displaying the

[PATCH v3 0/2] ARM: shmobile: Add support for RZ/A2

Introduce RZ/A2 (R7S9210) as an SoC that can be selected. There is no DT mainlined yet, so this is what the entry would look like for the BSID register: bsid: chipid@fcfe8004 { compatible = "renesas,bsid"; reg = <0xfcfe8004 4>; }; Chris Brandt

[PATCH 4/4] ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB

Adding pinctrl support for EtherAVB interface. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- This patch depends upon https://patchwork.kernel.org/patch/10546801/ --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8 1 file changed, 8 insertions(+) diff --git

[PATCH 3/4] ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ

Specify EtherAVB PHY IRQ in the board specific device tree, now that we have GPIO support. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts

[PATCH 1/4] gpio: rcar: Enhance gpio-ranges support

Enhance gpio-ranges to support more than one gpio-range. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- cat /sys/kernel/debug/pinctrl/e606.pin-controller-sh-pfc/gpio- GPIO ranges handled: 0: e605.gpio GPIOS [1001 - 1023] PINS [0 - 22] 0: e6051000.gpio GPIOS [978 - 1000] PINS

[PATCH 2/4] ARM: dts: r8a77470: Add GPIO support

Describe GPIO blocks in the R8A77470 device tree. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- arch/arm/boot/dts/r8a77470.dtsi | 90 + 1 file changed, 90 insertions(+) diff --git a/arch/arm/boot/dts/r8a77470.dtsi

[PATCH 0/4] Add GPIO and EAVB Pinctrl support

This patch series aims to add GPIO and EAVB Pinctrl support for RZ/G1C SoC. Biju Das (4): gpio: rcar: Enhance gpio-ranges support ARM: dts: r8a77470: Add GPIO support ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ ARM: dts: iwg23s-sbc: Add pinctl support for EtherAVB

RE: [PATCH] pinctrl: sh-pfc: r8a77470: Add EtherAVB pin groups

+ sergie > -Original Message- > From: Biju Das [mailto:biju@bp.renesas.com] > Sent: 27 July 2018 10:22 > To: Laurent Pinchart ; Geert > Uytterhoeven ; Linus Walleij > > Cc: Biju Das ; linux-renesas- > s...@vger.kernel.org; linux-g...@vger.kernel.org; Simon Horman > ; Chris Paterson ;

[PATCH] pinctrl: sh-pfc: r8a77470: Add EtherAVB pin groups

Add EtherAVB groups and functions definitions for R8A77470 SoC. Signed-off-by: Biju Das Reviewed-by: Fabrizio Castro --- This patch is based on the following discussion https://www.mail-archive.com/linux-renesas-soc@vger.kernel.org/msg27480.html and

Re: [PATCH] dmaengine: rcar-dmac: Make rcar_dmac_of_xlate() more robust

Hi Geert, Thank you for the patch. On Friday, 27 July 2018 11:44:47 EEST Geert Uytterhoeven wrote: > Add an upper bound check for the MID/RID value passed from DT via the > DMA spec. > > This avoids writing to reserved bits in the DMARS registers in case of > an out-of-range value in DT. Is

[PATCH] dmaengine: rcar-dmac: Make rcar_dmac_of_xlate() more robust

Add an upper bound check for the MID/RID value passed from DT via the DMA spec. This avoids writing to reserved bits in the DMARS registers in case of an out-of-range value in DT. Suggested-by: Renesas BSP team via Yoshihiro Shimoda Signed-off-by: Geert Uytterhoeven ---