Hi Niklas,
Thanks for your patch!
On Thu, Aug 30, 2018 at 11:39 PM Niklas Söderlund
wrote:
> Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a
> device_dma_parameters structure and filling in the max segment size. The
> size used is the result of a discussion with Renesas
Quoting Geert Uytterhoeven (2018-08-30 08:28:13)
> When trying to use I2C7 on R-Car E3:
>
> renesas-cpg-mssr e615.clock-controller: Cannot get module clock 1003:
> -2
> i2c-rcar e669.i2c: failed to add to PM domain always-on: -2
> i2c-rcar: probe of e669.i2c failed with
Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a
device_dma_parameters structure and filling in the max segment size. The
size used is the result of a discussion with Renesas hardware engineers
and unfortunately not found in the datasheet.
renesas_sdhi_internal_dmac
On Fri, Aug 24, 2018 at 04:52:43PM +0200, Wolfram Sang wrote:
> Jun Gao correctly identified a problem when freeing a DMA safe buffer [1],
> many
> thanks for that! However, I'd like to not introduce yet another function. So,
> I
> thought about changing the existing API to support the case of
When trying to use CMT for clockevents on R-Car gen3 SoCs, I noticed that
the maximum delta (in ns) for the broadcast timer was diplayed as 1000 in
/proc/timer_list. It turned out that when calculating it, the driver did
shift left 1 by 32 (causing what I think was undefined behaviour) getting
1
When trying to use I2C7 on R-Car E3:
renesas-cpg-mssr e615.clock-controller: Cannot get module clock 1003: -2
i2c-rcar e669.i2c: failed to add to PM domain always-on: -2
i2c-rcar: probe of e669.i2c failed with error -2
Unlike other R-Car Gen3 SoCs, R-Car E3 has more than
From: Takeshi Kihara
Add the device node for the external SCIF_CLK, and describe the clock
inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2,
which can increase serial clock accuracy.
The presence of the SCIF_CLK crystal and its clock frequency depend on
the actual board.
Use the SoC-specific CPG/MSSR include file to allow future use of
R8A77990_CLK_* symbols.
Replace the hardcoded power domain indices by R8A77990_PD_* symbols.
Signed-off-by: Geert Uytterhoeven
---
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 36 +++
1 file changed, 18
On Thu, Aug 30, 2018 at 02:38:07PM +0200, Geert Uytterhoeven wrote:
> The comments describing the non-default switch settings to use SATA are
> confusing: 'Off' refers to the switch position, not to the MD12 logic
> value, while the parentheses suggest otherwise. Rephrase to fix this.
>
>
On Thu, Aug 30, 2018 at 02:29:02PM +0200, Geert Uytterhoeven wrote:
> On Fri, Aug 24, 2018 at 12:50 PM Biju Das wrote:
> > Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
> > ---
> >
Hi Rob,
On Thu, Aug 30, 2018 at 3:49 PM Rob Herring wrote:
> On Thu, Aug 30, 2018 at 3:05 AM Geert Uytterhoeven
> wrote:
> > On Wed, Aug 29, 2018 at 2:52 AM Rob Herring wrote:
> > > On Mon, Aug 27, 2018 at 11:21:39AM -0500, Chris Brandt wrote:
> > > > Add support for the R7S9210 (RZ/A2) Clock
On Thu, Aug 30, 2018 at 09:44:23AM +, Phil Edworthy wrote:
> Hi Geert,
>
> On 28 August 2018 16:13, Geert Uytterhoeven wrote:
> > Replace the hardcoded clock indices by R9A06G032_CLK_* symbols.
> >
> > Signed-off-by: Geert Uytterhoeven
>
> Reviewed-by: Phil Edworthy
Thanks Geert, thanks
On Thu, Aug 30, 2018 at 03:04:48AM +, Yoshihiro Shimoda wrote:
> Hi Geert-san,
>
> > From: Geert Uytterhoeven, Sent: Tuesday, August 28, 2018 11:13 PM
> >
> > usb2_phy1 accidentally uses the same clock/reset as usb2_phy0.
> >
> > Fixes: b5857630a829a8d5 ("arm64: dts: renesas: r8a77965: add
On Thu, Aug 30, 2018 at 03:04:06AM +, Yoshihiro Shimoda wrote:
> Hi Geert-san,
>
> > From: Geert Uytterhoeven, Sent: Tuesday, August 28, 2018 10:57 PM
> >
> > Should be "renesas,usbhs-r8a77965", not "renesas,usbhs-r8a7796".
> >
> > Fixes: a06e8af801760a98 ("arm64: dts: renesas: r8a77965:
On Wed, Aug 29, 2018 at 05:27:58PM +0200, Niklas Söderlund wrote:
> Hi Geert,
>
> Thanks for your patch.
>
> On 2018-08-28 16:14:44 +0200, Geert Uytterhoeven wrote:
> > To preserve alphabetical sort order.
> >
> > Fixes: 4c529600eef0a6b7 ("arm64: dts: renesas: r8a77965: Add R-Car Gen3
> >
On Tue, Aug 28, 2018 at 04:56:46PM +0200, Geert Uytterhoeven wrote:
> Refresh the defconfig for Renesas ARM boards:
> - Move options that have moved,
> - Remove CONFIG_HAVE_ARM_ARCH_TIMER (auto-enabled),
> - Remove ENABLE_WARN_DEPRECATED (removed).
>
> Signed-off-by: Geert Uytterhoeven
On Tue, Aug 28, 2018 at 04:47:52PM +0200, Geert Uytterhoeven wrote:
> Enable support for the CryptoCell core present in some R-Car Gen3 SoCs,
> which allows to offload crypto operations.
>
> Signed-off-by: Geert Uytterhoeven
Thanks,
I have applied this to the topic/renesas-defconfig branch
On Tue, Aug 28, 2018 at 04:46:15PM +0200, Geert Uytterhoeven wrote:
> Refresh the defconfig for Renesas R-Car Gen3 boards:
> - Move options that have moved,
> - Remove CONFIG_PCIE_DW_PLAT_HOST (auto-disabled),
> - Remove CONFIG_DEBUG_FS (auto-enabled).
>
> Signed-off-by: Geert Uytterhoeven
On Thu, Aug 30, 2018 at 3:05 AM Geert Uytterhoeven wrote:
>
> Hi Rob,
>
> On Wed, Aug 29, 2018 at 2:52 AM Rob Herring wrote:
> > On Mon, Aug 27, 2018 at 11:21:39AM -0500, Chris Brandt wrote:
> > > Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
> > > Standby.
> > >
> > > The
Hi Simon,
On Thu, Aug 30, 2018 at 3:08 PM Simon Horman wrote:
> On Tue, Aug 28, 2018 at 04:10:59PM +0200, Geert Uytterhoeven wrote:
> > Signed-off-by: Geert Uytterhoeven
> > ---
> > arch/arm64/boot/dts/renesas/r8a774a1.dtsi| 4 +-
> > arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 16
On Tue, Aug 28, 2018 at 04:15:40PM +0200, Geert Uytterhoeven wrote:
> To preserve alphabetical sort order.
>
> Fixes: 4edac426aff11a37 ("arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI
> support")
> Signed-off-by: Geert Uytterhoeven
Thanks Geert, applied for v4.20.
On Tue, Aug 28, 2018 at 04:10:59PM +0200, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven
> ---
> arch/arm64/boot/dts/renesas/r8a774a1.dtsi| 4 +-
> arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 16 +++
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 48
On Wed, Aug 22, 2018 at 01:14:09PM +0200, Simon Horman wrote:
> On Sun, Aug 12, 2018 at 03:31:49PM +0200, Eugeniu Rosca wrote:
> > This is based on the existing KF device tree sources:
> > $ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts
> > arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
> >
On Mon, Aug 27, 2018 at 09:28:09PM +0200, Eugeniu Rosca wrote:
> Hi Simon, hi Geert,
>
> On Mon, Aug 27, 2018 at 02:44:47PM +0200, Simon Horman wrote:
> > On Thu, Aug 23, 2018 at 10:52:09AM +0200, Geert Uytterhoeven wrote:
> > > On Fri, Aug 17, 2018 at 3:53 PM Kieran Bingham
> > > wrote:
> > > >
Hi Wolfram,
On Tue, Aug 21, 2018 at 3:41 PM Wolfram Sang wrote:
> > > +/* MD12 (SW12-7) must be set 'Off' which is not the default! */
> >
> > Upon reading this again, I think this comment is confusing: the 'Off' refers
> > to the switch position, not to the MD12 logic value, while the
The comments describing the non-default switch settings to use SATA are
confusing: 'Off' refers to the switch position, not to the MD12 logic
value, while the parentheses suggest otherwise. Rephrase to fix this.
Fixes: bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA")
The comments describing the non-default switch settings to use SATA are
confusing: 'Off' refers to the switch position, not to the MD12 logic
value, while the parentheses suggest otherwise. Rephrase to fix this.
Signed-off-by: Geert Uytterhoeven
Acked-by: Wolfram Sang
---
On Mon, Aug 27, 2018 at 09:54:35PM +0300, Sergei Shtylyov wrote:
> Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
> board.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov
> Signed-off-by: Sergei Shtylyov
Thanks
On Mon, Aug 27, 2018 at 09:53:40PM +0300, Sergei Shtylyov wrote:
> Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
> tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov
> Signed-off-by: Sergei Shtylyov
>
On 30 August 2018 at 14:16, Wolfram Sang
wrote:
> This variable is unused now after some refactoring.
>
> Signed-off-by: Wolfram Sang
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/tmio_mmc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On 23 August 2018 at 06:44, Masahiro Yamada
wrote:
> renesas_sdhi_clk_start() and renesas_sdhi_clk_stop() are now only
> called from renesas_sdhi_set_clock(). Merge them.
>
> Signed-off-by: Masahiro Yamada
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> Changes in v3: None
> Changes in
On 30 August 2018 at 14:14, Wolfram Sang
wrote:
> Concise, but still readable.
>
> Signed-off-by: Wolfram Sang
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/tmio_mmc.c | 11 +++
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git
On 30 August 2018 at 01:32, Niklas Söderlund
wrote:
> Hi,
>
> These patches triggers a retune if a SCC error is detected. They where
> ported from the renesas BSP. Masaharu-san did all the real work I just
> ported them to upstream and did small fixups.
>
> These patches where broken out of my
On Tue, Aug 28, 2018 at 03:17:39PM +0200, Simon Horman wrote:
> On Fri, Aug 24, 2018 at 11:43:48AM +0100, Biju Das wrote:
> > Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
>
> Thanks,
>
> This looks fine to me but I
On Fri, Aug 24, 2018 at 12:50 PM Biju Das wrote:
> Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
> ---
> arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 73
> +++
> 1 file changed, 73
On Tue, Aug 28, 2018 at 03:42:05PM +0200, Simon Horman wrote:
> On Fri, Aug 24, 2018 at 11:43:49AM +0100, Biju Das wrote:
> > Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
>
> Thanks,
>
> This looks fine to
On Fri, Aug 24, 2018 at 11:43:47AM +0100, Biju Das wrote:
> Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi.
>
> Signed-off-by: Biju Das
> Reviewed-by: Fabrizio Castro
Thanks, applied for v4.20.
On Mon, Aug 27, 2018 at 11:53:35AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 03:22:46PM +0100, Fabrizio Castro wrote:
> > From: Chris Paterson
> >
> > Add the device nodes for both RZ/G2M CAN channels.
> >
> > Signed-off-by: Chris Paterson
> > Reviewed-by: Biju Das
>
> Thanks,
>
On Mon, Aug 27, 2018 at 11:48:09AM +0200, Simon Horman wrote:
> On Fri, Aug 24, 2018 at 11:21:14AM +0100, Fabrizio Castro wrote:
> > Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly
> > to what was done for the r8a7796 with commit 41dbbf0c5b4e
> > ("arm64: dts: r8a7796: Add FCPF and
On Mon, Aug 27, 2018 at 11:32:52AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 02:43:07PM +0100, Fabrizio Castro wrote:
> > From: Biju Das
> >
> > Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1).
> >
> > This work is based on similar work done on the R8A7796 SoC
> > by Kuninori
On Mon, Aug 27, 2018 at 11:12:39AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 02:43:06PM +0100, Fabrizio Castro wrote:
> > This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1)
> > device tree.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
>
>
On Mon, Aug 27, 2018 at 11:08:33AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 02:43:05PM +0100, Fabrizio Castro wrote:
> > From: Biju Das
> >
> > This patch adds definitions for L2 cache for the Cortex-A53 CPU
> > cores (512 KiB in size, organized as 32 KiB x 16 ways), adds
> >
On Mon, Aug 27, 2018 at 11:05:52AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 02:43:04PM +0100, Fabrizio Castro wrote:
> > From: Biju Das
> >
> > Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC.
> >
> > Based on several similar patches of the R8A7796 device tree
> >
On Mon, Aug 27, 2018 at 11:02:36AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 02:43:03PM +0100, Fabrizio Castro wrote:
> > Add r8a774a1 IPMMU nodes.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
>
> Thanks,
>
> This looks fine to me but I will wait to see if there
On Mon, Aug 27, 2018 at 10:54:08AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 02:43:02PM +0100, Fabrizio Castro wrote:
> > From: Biju Das
> >
> > Add thermal support for R8A774A1 (RZ/G2M) SoC.
> >
> > Based on the work done for r8a7796 SoC.
> >
> > Signed-off-by: Biju Das
> >
On Thu, Aug 23, 2018 at 02:43:00PM +0100, Fabrizio Castro wrote:
> Add SDHI nodes to the DT of the r8a774a1 SoC.
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Biju Das
Thanks again, applied for v4.20.
On Mon, Aug 27, 2018 at 10:51:35AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 02:43:01PM +0100, Fabrizio Castro wrote:
> > From: Biju Das
> >
> > Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
> > devices nodes to the r8a774a1 device tree.
> >
> > Signed-off-by: Biju
On Mon, Aug 27, 2018 at 10:00:20AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 03:18:18PM +0100, Fabrizio Castro wrote:
> > Add GPIO device nodes to the DT of the r8a774a1 SoC.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
> > ---
> >
> > This patch depends on:
> >
On Tue, Aug 28, 2018 at 1:11 PM Laurent Pinchart
wrote:
> This patch adds DU pins, groups and function for the R8A77990 (E3) SoC.
>
> Signed-off-by: Laurent Pinchart
> ---
> Changes since v1:
>
> - Add DU_CLKIN0
Thanks for the update!
Reviewed-by: Geert Uytterhoeven
i.e. queued in
On Mon, Aug 27, 2018 at 09:47:37AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 03:13:16PM +0100, Fabrizio Castro wrote:
> > This patch adds pinctrl device node for R8A774A1 SoC.
> >
> > Signed-off-by: Fabrizio Castro
> > Reviewed-by: Biju Das
> > ---
> >
> > This patch depends on:
> >
On Fri, Aug 24, 2018 at 11:05:03AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 09:58:51AM +0100, Biju Das wrote:
> > Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
> > RZ/G2M (r8a774a1) SoC.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
> >
This variable is unused now after some refactoring.
Signed-off-by: Wolfram Sang
---
drivers/mmc/host/tmio_mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index 0ae100e62b57..29bda8224ae7 100644
---
On Tue, Aug 28, 2018 at 02:20:44PM +0200, Simon Horman wrote:
> On Fri, Aug 24, 2018 at 09:06:49AM +, Fabrizio Castro wrote:
> > Hello Simon,
> >
> > Thank you for your feedback!
> >
> > > Subject: Re: [PATCH 4/5] arm64: dts: renesas: r8a774a1: Add Ethernet AVB
> > > node
> > >
> > > On
On Fri, Aug 24, 2018 at 10:55:13AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 09:58:49AM +0100, Biju Das wrote:
> > Add support for the Interrupt Controller for External Devices
> > (INTC-EX) on RZ/G2M.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
>
> Thanks,
>
>
On Fri, Aug 24, 2018 at 10:52:57AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 09:58:48AM +0100, Biju Das wrote:
> > From: Fabrizio Castro
> >
> > Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
> > incl. clocks, power domains and DMAs.
> > According to the HW user
Concise, but still readable.
Signed-off-by: Wolfram Sang
---
drivers/mmc/host/tmio_mmc.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index 0ae9ba1ee01b..0ae100e62b57 100644
---
On Fri, Aug 24, 2018 at 10:38:59AM +0200, Simon Horman wrote:
> On Thu, Aug 23, 2018 at 09:58:47AM +0100, Biju Das wrote:
> > Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.
> >
> > Signed-off-by: Biju Das
> > Reviewed-by: Fabrizio Castro
>
> Thanks,
>
> This looks fine to me but I
> We could do that but then we can't reset the struct device dma_parms
> member to NULL.
I think it is fine to skip this. From the device_add docs:
* Do not call this routine or device_register() more than once for
* any device structure. The driver model core is not designed to work
*
Hi Wolfram,
Thanks for your feedback.
On 2018-08-30 11:49:12 +0200, Wolfram Sang wrote:
> Hi Niklas,
>
> > + if (!dev->dma_parms) {
> > + dev->dma_parms = kzalloc(sizeof(*dev->dma_parms), GFP_KERNEL);
>
> Can't we use devm_kzalloc and skip the custom remove function?
We could do
On Thu, Aug 30, 2018 at 01:32:07AM +0200, Niklas Söderlund wrote:
> From: Masaharu Hayakawa
>
> SDR104, HS200 and HS400 need to check for SCC error. If SCC error is
> detected, retuning is necessary.
>
> Signed-off-by: Masaharu Hayakawa
> [Niklas: update commit message]
> Signed-off-by: Niklas
On Thu, Aug 30, 2018 at 01:32:05AM +0200, Niklas Söderlund wrote:
> Add a helper to allow host drivers checking if a retune is in progress.
>
> Signed-off-by: Niklas Söderlund
Reviewed-by: Wolfram Sang
Tested-by: Wolfram Sang
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On Thu, Aug 30, 2018 at 01:32:06AM +0200, Niklas Söderlund wrote:
> From: Masaharu Hayakawa
>
> Checking for SCC error during retuning is unnecessary.
>
> Signed-off-by: Masaharu Hayakawa
> [Niklas: fix small style issue]
> Signed-off-by: Niklas Söderlund
Reviewed-by: Wolfram Sang
- UART0 was missing the bus clock ("apb_pclk").
- Now that the relevant rzn1 bindings have been added, replace the Synopsys
compat string with the rzn1 strings.
- Add all the other UARTs.
Signed-off-by: Phil Edworthy
---
arch/arm/boot/dts/r9a06g032.dtsi | 83
Hi Niklas,
> + if (!dev->dma_parms) {
> + dev->dma_parms = kzalloc(sizeof(*dev->dma_parms), GFP_KERNEL);
Can't we use devm_kzalloc and skip the custom remove function?
Thanks,
Wolfram
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Hi Geert,
On 28 August 2018 16:13, Geert Uytterhoeven wrote:
> Replace the hardcoded clock indices by R9A06G032_CLK_* symbols.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Phil Edworthy
Thanks!
Phil
Hello!
On 8/30/2018 5:39 AM, Nguyen An Hoan wrote:
From: Hoan Nguyen An
About the formula for temperature calculation
[reg] = [temp] * a + b <=> [temp] = ([reg] - b) / a
Using "(mcelsius * tsc-> coef.aX) / 1000" instead of "DIV_ROUND_CLOSEST(mcelsius, 1000)
* tsc-> coef.aX"
to avoid and
2018-08-30 11:16 GMT+02:00 Daniel Lezcano :
>
> [Added Arnd Bergmann, Bartosz Golaszewski and Mark Brown]
>
> On 30/08/2018 10:48, Geert Uytterhoeven wrote:
>> Hi Daniel,
>
> [ ... ]
>
>>> Yeah, I got this point. But it is the meaning of your sentence: "...
>>> which causes issues with complex
[Added Arnd Bergmann, Bartosz Golaszewski and Mark Brown]
On 30/08/2018 10:48, Geert Uytterhoeven wrote:
> Hi Daniel,
[ ... ]
>> Yeah, I got this point. But it is the meaning of your sentence: "...
>> which causes issues with complex dependencies.".
>>
>> It is ambiguous *what* causes the
Hi Daniel,
On Thu, Aug 30, 2018 at 10:37 AM Daniel Lezcano
wrote:
> On 30/08/2018 10:27, Geert Uytterhoeven wrote:
> > On Thu, Aug 30, 2018 at 10:09 AM Daniel Lezcano
> > wrote:
> >> On 30/08/2018 09:54, Geert Uytterhoeven wrote:
> >>> On Wed, Aug 29, 2018 at 6:26 PM Daniel Lezcano
> >>>
Hi Simon,
On Tue, Aug 28, 2018 at 1:49 PM Simon Horman wrote:
> This is intended as a submission to LTSI-4.14. It is the backport
> of a fix for the R-Car I2C driver, and its dependency, both of which
> are present in linux-next 20180821.
>
> This pull-request is based on
> "[GIT PULL LTSI-4.14]
On 30/08/2018 10:27, Geert Uytterhoeven wrote:
> Hi Daniel,
>
> On Thu, Aug 30, 2018 at 10:09 AM Daniel Lezcano
> wrote:
>> On 30/08/2018 09:54, Geert Uytterhoeven wrote:
>>> On Wed, Aug 29, 2018 at 6:26 PM Daniel Lezcano
>>> wrote:
On 29/08/2018 17:44, Chris Brandt wrote:
> On
Hi Daniel,
On Thu, Aug 30, 2018 at 10:09 AM Daniel Lezcano
wrote:
> On 30/08/2018 09:54, Geert Uytterhoeven wrote:
> > On Wed, Aug 29, 2018 at 6:26 PM Daniel Lezcano
> > wrote:
> >> On 29/08/2018 17:44, Chris Brandt wrote:
> >>> On Wednesday, August 29, 2018 1, Daniel Lezcano wrote:
> Can
On 30/08/2018 09:54, Geert Uytterhoeven wrote:
> Hi Daniel,
>
> On Wed, Aug 29, 2018 at 6:26 PM Daniel Lezcano
> wrote:
>> On 29/08/2018 17:44, Chris Brandt wrote:
>>> On Wednesday, August 29, 2018 1, Daniel Lezcano wrote:
Can the boot constraints [1] solve this issue instead of the changes
Hi Rob,
On Wed, Aug 29, 2018 at 2:52 AM Rob Herring wrote:
> On Mon, Aug 27, 2018 at 11:21:39AM -0500, Chris Brandt wrote:
> > Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module
> > Standby.
> >
> > The Module Standby HW in the RZ/A series is very close to R-Car HW, except
> >
Hi Laurent,
On Wed, Aug 29, 2018 at 11:12 AM Laurent Pinchart
wrote:
> On Tuesday, 28 August 2018 15:10:52 EEST Geert Uytterhoeven wrote:
> > On Wed, Jun 13, 2018 at 10:11 PM Sergei Shtylyov wrote:
> > > Describe the interconnected FCPVD0, VSPD0, DU, and LVDS0 devices in the
> > > R8A77980
Hi Hoan,
On Wed, Aug 29, 2018 at 11:33 AM Nguyen An Hoan wrote:
> From: Hoan Nguyen An
>
> Add PWM-2 channel(CN28 - pin30) support for Salvator-X
Thanks for your patch!
Please explain why this is useful. Usually we do not enable random functionality
on expansion connectors.
In this case,
Hi Daniel,
On Wed, Aug 29, 2018 at 6:26 PM Daniel Lezcano
wrote:
> On 29/08/2018 17:44, Chris Brandt wrote:
> > On Wednesday, August 29, 2018 1, Daniel Lezcano wrote:
> >> Can the boot constraints [1] solve this issue instead of the changes you
> >> are proposing ?
> >>
> >> [1]
Hi Hoan,
On Thu, Aug 30, 2018 at 4:39 AM Nguyen An Hoan wrote:
> From: Hoan Nguyen An
>
> About the formula for temperature calculation
> [reg] = [temp] * a + b <=> [temp] = ([reg] - b) / a
>
> Using "(mcelsius * tsc-> coef.aX) / 1000" instead of
> "DIV_ROUND_CLOSEST(mcelsius, 1000) * tsc->
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