On Tue, Jul 17, 2018 at 12:12:14PM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Tue, Jul 17, 2018 at 11:59 AM Simon Horman wrote:
> > On Fri, Jul 13, 2018 at 10:33:17AM +0200, Geert Uytterhoeven wrote:
> > > On Fri, Jul 13, 2018 at 10:19 AM Geert Uytterhoeven
> > > wrote:
> > > > On Fri,
Hi Simon,
On Tue, Jul 17, 2018 at 11:59 AM Simon Horman wrote:
> On Fri, Jul 13, 2018 at 10:33:17AM +0200, Geert Uytterhoeven wrote:
> > On Fri, Jul 13, 2018 at 10:19 AM Geert Uytterhoeven
> > wrote:
> > > On Fri, Jul 13, 2018 at 10:08 AM Simon Horman wrote:
> > > > On Thu, Jul 12, 2018 at
On Fri, Jul 13, 2018 at 10:33:17AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Fri, Jul 13, 2018 at 10:19 AM Geert Uytterhoeven
> wrote:
> > On Fri, Jul 13, 2018 at 10:08 AM Simon Horman wrote:
> > > On Thu, Jul 12, 2018 at 06:08:57PM +0200, Geert Uytterhoeven wrote:
> > > > R-Mobile
Hi Chris,
On Fri, Jul 13, 2018 at 2:22 PM Chris Brandt wrote:
> On Friday, July 13, 2018, linux-renesas-soc-ow...@vger.kernel.org wrote:
> > > Exactly what the level of software support is available for the ARM
> > > timers at this point I'm not so sure about.
> >
> > Using the TWD timer indeed
On Friday, July 13, 2018, linux-renesas-soc-ow...@vger.kernel.org wrote:
> > Exactly what the level of software support is available for the ARM
> > timers at this point I'm not so sure about.
>
> Using the TWD timer indeed has two issues:
> - It's available on multi-core Cortex-A9 SoCs only,
>
Hi Simon,
On Fri, Jul 13, 2018 at 10:19 AM Geert Uytterhoeven
wrote:
> On Fri, Jul 13, 2018 at 10:08 AM Simon Horman wrote:
> > On Thu, Jul 12, 2018 at 06:08:57PM +0200, Geert Uytterhoeven wrote:
> > > R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs have Cortex-A7 and/or
> > > Cortex-A15 CPU cores,
Hi Simon,
On Fri, Jul 13, 2018 at 10:08 AM Simon Horman wrote:
> On Thu, Jul 12, 2018 at 06:08:57PM +0200, Geert Uytterhoeven wrote:
> > R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs have Cortex-A7 and/or
> > Cortex-A15 CPU cores, all of which have ARM architectured timers.
> >
> > Force use of the
On Thu, Jul 12, 2018 at 06:08:57PM +0200, Geert Uytterhoeven wrote:
> R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs have Cortex-A7 and/or
> Cortex-A15 CPU cores, all of which have ARM architectured timers.
>
> Force use of the ARM architectured timer on these SoCs.
> This allows to:
> - Remove the
Hi Magnus,
On Fri, Jul 13, 2018 at 5:11 AM Magnus Damm wrote:
> On Fri, Jul 13, 2018 at 1:08 AM, Geert Uytterhoeven
> wrote:
> > R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs have Cortex-A7 and/or
> > Cortex-A15 CPU cores, all of which have ARM architectured timers.
> >
> > Force use of the ARM
On Fri, Jul 13, 2018 at 1:08 AM, Geert Uytterhoeven
wrote:
> R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs have Cortex-A7 and/or
> Cortex-A15 CPU cores, all of which have ARM architectured timers.
>
> Force use of the ARM architectured timer on these SoCs.
> This allows to:
> - Remove the calls to
R-Mobile APE6, R-Car Gen2, and RZ/G1 SoCs have Cortex-A7 and/or
Cortex-A15 CPU cores, all of which have ARM architectured timers.
Force use of the ARM architectured timer on these SoCs.
This allows to:
- Remove the calls to shmobile_init_delay() from the corresponding
machine vectors,
-
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