On Tue, Feb 13, 2018 at 12:38:44PM +0100, Simon Horman wrote:
> On Wed, Feb 07, 2018 at 11:21:44PM +0100, Wolfram Sang wrote:
> >
> > > + /* Reset HS400 mode */
> > > + sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
> > > + sd_ctrl_read16(host, CTL_SDIF_MODE));
> > > + sd_scc_write
On Wed, Feb 07, 2018 at 11:21:44PM +0100, Wolfram Sang wrote:
>
> > + /* Reset HS400 mode */
> > + sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
> > + sd_ctrl_read16(host, CTL_SDIF_MODE));
> > + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
> > +
> + /* Reset HS400 mode */
> + sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
> + sd_ctrl_read16(host, CTL_SDIF_MODE));
> + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
> +~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
> +
From: Masaharu Hayakawa
This patch adds processing for selecting HS400 mode.
Signed-off-by: Masaharu Hayakawa
Signed-off-by: Simon Horman
---
v2 [Simon Horman]
* Updated to new version from BSP v3.6.0
* Dropped 4 and 8 tap differentiation as all SoCs currently supported
by the driver in upst