Re: [PATCH v2 3/5] v4l: vsp1: Map the DL and video buffers through the proper bus master

Hi Laurent, Thanks for the patch: On 17/05/17 00:20, Laurent Pinchart wrote: > From: Magnus Damm > > On Gen2 hardware the VSP1 is a bus master and accesses the display list > and video buffers through DMA directly. On Gen3 hardware, however, > memory accesses go through

[PATCH v2 3/5] v4l: vsp1: Map the DL and video buffers through the proper bus master

From: Magnus Damm On Gen2 hardware the VSP1 is a bus master and accesses the display list and video buffers through DMA directly. On Gen3 hardware, however, memory accesses go through a separate IP core called FCP. The VSP1 driver unconditionally maps DMA buffers through