Hi Ulf, Wolfram
On 2018-11-19 14:33:58 +0100, Wolfram Sang wrote:
>
> > Sure, no problem. I drop this and the other series then.
>
> Thanks, Ulf!
>
Thanks for looking out for me here, I will fly home tomorrow so I hope
to get a new versions of these series out late this week.
--
Regards,
Ni
> Sure, no problem. I drop this and the other series then.
Thanks, Ulf!
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On 19 November 2018 at 13:14, Wolfram Sang wrote:
>
>> I noticed there were a minor comment from Yamada-san, however I
>> decided to pick this as is and leave further improvements to be made
>> on top.
>
> Can I vote for waiting until Niklas comes back from Plumbers and have a
> proper V2 applied
> I noticed there were a minor comment from Yamada-san, however I
> decided to pick this as is and leave further improvements to be made
> on top.
Can I vote for waiting until Niklas comes back from Plumbers and have a
proper V2 applied instead? Makes backporting easier.
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On 1 November 2018 at 00:05, Niklas Söderlund
wrote:
> From: Niklas Söderlund
>
> Hi,
>
> While looking at the Renesas BSP kernel I found patches which improves
> the state of the hardware at probe and after runtime resume.
>
> Patch 1/3 make sure the module clock is enabled after resuming before
All patches tested on M3N, H2, and E2.
Tested-by: Wolfram Sang
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So, we agreed on this series during our Renesas SDHI hackathon.
Comments / testing from Yamada-san would be very welcome because we
really don't want to cause regressions on his hardware.
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From: Niklas Söderlund
Hi,
While looking at the Renesas BSP kernel I found patches which improves
the state of the hardware at probe and after runtime resume.
Patch 1/3 make sure the module clock is enabled after resuming before
register are accessed. Patch 2/3 is the real change in this series
