The processor manual prescribes to clear reset of LVDS interface in CPG/MSSR
module before display on, and to assert the same reset line at display off
time, to have the module resuming in a known state.
The module is said to be in "standby state" at initialization time, and this
requires, accordi
Hello Jacopo,
Thank you for the patch.
On Wednesday, 1 August 2018 17:26:36 EEST Jacopo Mondi wrote:
> The processor manual prescribes to clear reset of LVDS interface in CPG/MSSR
> module before display on, and to assert the same reset line at display off
> time, to have the module resuming in a