Hi Chris,
On Thu, Nov 29, 2018 at 2:07 PM Chris Brandt wrote:
> Basic support for the RZ/A2 (R7S9210) SoC.
>
> Signed-off-by: Chris Brandt
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm/boot/dts/r7s9210.dtsi
> @@ -0,0 +1,211 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + *
From: Geert Uytterhoeven [mailto:ge...@linux-m68k.org]
Sent: Friday, November 30, 2018 11:03 AM
> BTW, I'd be surprised the hardware address decoder would route all
> addresses in the range 0xe803b000..0xe803b02f to the OSTM.
> 0xe803b000..0xe803b03f sounds more logical to me, as it requires less
Hi Simon,
On Fri, Nov 30, 2018 at 1:23 PM Simon Horman wrote:
> On Fri, Nov 30, 2018 at 12:04:57PM +, Chris Brandt wrote:
> > On Friday, November 30, 2018, Simon Horman wrote:
> > > > + ostm0: timer@e803b000 {
> > > > + compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> > > > +
On Fri, Nov 30, 2018 at 12:04:57PM +, Chris Brandt wrote:
> Hi Simon,
>
>
> On Friday, November 30, 2018, Simon Horman wrote:
> > > + cpg: clock-controller@fcfe0020 {
> > > + compatible = "renesas,r7s9210-cpg-mssr";
> > > + reg = <0xfcfe0010 0x455>;
> >
> > There is a
Hi Simon,
On Friday, November 30, 2018, Simon Horman wrote:
> > + cpg: clock-controller@fcfe0020 {
> > + compatible = "renesas,r7s9210-cpg-mssr";
> > + reg = <0xfcfe0010 0x455>;
>
> There is a discrepancy here between the base address, fcfe0020
> and the start address of
On Thu, Nov 29, 2018 at 08:05:58AM -0500, Chris Brandt wrote:
> Basic support for the RZ/A2 (R7S9210) SoC.
>
> Signed-off-by: Chris Brandt
> ---
> arch/arm/boot/dts/r7s9210.dtsi | 211
> +
> 1 file changed, 211 insertions(+)
> create mode 100644
