RE: [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions

Hi Geert-san, Thank you for the review! > From: Geert Uytterhoeven, Sent: Thursday, April 12, 2018 9:23 PM > > Hi Shimoda-san, > > On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda > wrote: > > --- /dev/null > > +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h > > @@ -0,0 +1,63 @@ > > +/

Re: [PATCH 1/2] clk: renesas: Add r8a77990 CPG Core Clock Definitions

Hi Shimoda-san, On Wed, Apr 11, 2018 at 11:37 AM, Yoshihiro Shimoda wrote: > From: Takeshi Kihara > > This patch adds all R-Car E3 Clock Pulse Generator Core Clock Outputs. > > Note that internal CPG clocks (S0, S1, S2, S3, SDSRC) are not included, > as they are used as internal clock sources on