Hi Laurent
> > > The parent clock isn't documented in the datasheet, use S2D1 as a best
> > > guess for now.
> >
> > Would you be able to find out what the parent clock is for the FCP and LVDS
> > (patch 2/9) clocks ?
>
> Thanks !
> I asked it to HW team
It is too late information for you
LV
Hi Geert,
On Thursday 03 March 2016 12:56:29 Geert Uytterhoeven wrote:
> On Thu, Mar 3, 2016 at 11:49 AM, Laurent Pinchart wrote:
> > On Thursday 03 March 2016 08:37:02 Kuninori Morimoto wrote:
> >> - s2d2 (for 200MHz)
> >> - s2d1 (for 400MHz)
> >
> > Thank you for the informati
Hi Laurent,
On Thu, Mar 3, 2016 at 11:49 AM, Laurent Pinchart
wrote:
> On Thursday 03 March 2016 08:37:02 Kuninori Morimoto wrote:
>> - s2d2 (for 200MHz)
>> - s2d1 (for 400MHz)
>> >>>
>> >>> Thank you for the information. Do you mean that different FCP instances
>> >>> use different c
Hi Morimoto-san,
On Thursday 03 March 2016 08:37:02 Kuninori Morimoto wrote:
> Hi Laurent
>
> - s2d2 (for 200MHz)
> - s2d1 (for 400MHz)
> >>>
> >>> Thank you for the information. Do you mean that different FCP instances
> >>> use different clocks ? If so, could you tell us which clock
Hi Laurent
> > >> - s2d2 (for 200MHz)
> > >> - s2d1 (for 400MHz)
> > >
> > > Thank you for the information. Do you mean that different FCP instances
> > > use different clocks ? If so, could you tell us which clock is used by
> > > each instance in th H3 ES1 ?
> >
> > Sorry for my confusable
Hi Morimoto-sa,
On Thursday 03 March 2016 07:19:20 Kuninori Morimoto wrote:
> Hi Laurent
>
> >> It seems FCP clock is based on each SoC
> >> In H3 ES1 case, it is using
> >>
> >> - s2d2 (for 200MHz)
> >> - s2d1 (for 400MHz)
> >
> > Thank you for the information. Do you mean that different FCP
Hi Laurent
> > It seems FCP clock is based on each SoC
> > In H3 ES1 case, it is using
> > - s2d2 (for 200MHz)
> > - s2d1 (for 400MHz)
>
> Thank you for the information. Do you mean that different FCP instances use
> different clocks ? If so, could you tell us which clock is used by each
> i
Hi Morimoto-san,
On Thursday 03 March 2016 00:17:54 Kuninori Morimoto wrote:
> Hi Laurent
>
> >>> The parent clock isn't documented in the datasheet, use S2D1 as a best
> >>> guess for now.
> >>
> >> Would you be able to find out what the parent clock is for the FCP and
> >> LVDS (patch 2/9) clo
Hi Laurent
> > > The parent clock isn't documented in the datasheet, use S2D1 as a best
> > > guess for now.
> >
> > Would you be able to find out what the parent clock is for the FCP and LVDS
> > (patch 2/9) clocks ?
It seems FCP clock is based on each SoC
In H3 ES1 case, it is using
- s2d2
Hi Laurent
> > The parent clock isn't documented in the datasheet, use S2D1 as a best
> > guess for now.
>
> Would you be able to find out what the parent clock is for the FCP and LVDS
> (patch 2/9) clocks ?
Thanks !
I asked it to HW team
> Feel free to tell the documentation team that your l
Hi Morimoto-san,
On Friday 12 February 2016 04:00:42 Laurent Pinchart wrote:
> The parent clock isn't documented in the datasheet, use S2D1 as a best
> guess for now.
Would you be able to find out what the parent clock is for the FCP and LVDS
(patch 2/9) clocks ?
Feel free to tell the documenta
Hi Geert,
On Monday 15 February 2016 10:22:22 Geert Uytterhoeven wrote:
> On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart wrote:
> > The parent clock isn't documented in the datasheet, use S2D1 as a best
> > guess for now.
>
> Looks like a good guess...
> I assume the driver doesn't depend on t
On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart
wrote:
> The parent clock isn't documented in the datasheet, use S2D1 as a best
> guess for now.
Looks like a good guess...
I assume the driver doesn't depend on the clock rate?
> Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
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