On Thu, Jul 8, 2010 at 12:39 PM, Jassi Brar wrote:
> On Thu, Jul 8, 2010 at 12:05 PM, Kyungmin Park wrote:
>
>> 3. Aquila & goni board support.
>> If possible all feature are included at current maineline kernel
>> implemented.
>
> Without doubt it's pleasing to see so many people involved pus
On Thu, Jul 8, 2010 at 12:05 PM, Kyungmin Park wrote:
> 3. Aquila & goni board support.
> If possible all feature are included at current maineline kernel
> implemented.
Without doubt it's pleasing to see so many people involved pushing support
for Samsung's SoCs and machines based upon them.
Hi Kukjin,
Before next merge window, I hope these features will be included.
If your team is done already, please reply it. If not, our team will do it.
1. High-resolution timer using timer 4 and systimer.
other timer 1, 2, 3, is used
2. Basic suspend & resume feature.
No clock gating, a
Russell King wrote:
>
> On Wed, Jul 07, 2010 at 08:27:53AM +0900, Kukjin Kim wrote:
> > Russell King wrote:
> > > What is the spacing of chunks of memory, and minimum alignment of
those
> > > chunks in physical address space?
> >
> > Some S5PC110(MCP D-type) has only available 80MiB in a bank.
> >
On Wed, Jul 07, 2010 at 01:02:12AM +0100, Ben Dooks wrote:
> Re-send of previous set, with corrected patches.
Hm, what tree are these going through? Do you need me to take them
through the linux-usb tree? Or are they going through a
platform-specific one somewhere?
confused,
greg k-h
--
To uns
Fix a problem where we have been underestimating the space available in
the IN PTX/NPTX FIFOs by assuming that they where simply word aligned
instead of in number-of-words. This means all length calculations need
to be multiplied-by-4.
Note, we do not change the information about fifo size or star
Limit the IN FIFO write to a single packet per attempt at writing,
as per the specifications and ensure that we don't return fifo-full
so that we can continue writing packets if we have the space.
Signed-off-by: Ben Dooks
---
drivers/usb/gadget/s3c-hsotg.c | 11 +++
1 files changed, 11
Add support for the dedicated FIFO mode on newer SoCs such as the S5PV210
partly to improve support and to fix the bug where any non-EP0 IN endpoint
requires its own FIFO allocation.
To fix this, we ensure that any non-zero IN endpoint is given a TXFIFO
using the same allocation method as the peri
From: Maurus Cuelenaere
The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz.
This patch adds support to the USB driver for setting the correct register bit
according to the given clock.
This depends on the following patch:
[PATCH] ARM: S3C64XX: Add USB external clock defi
The maximum length for any EP0 IN request on EP0 is 127 bytes, not 128
as the driver currently has it.
Signed-off-by: Ben Dooks
---
drivers/usb/gadget/s3c-hsotg.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hs
The USB documentation suggest that the FIFOs should be reset when a
bus reset event happens. Use the s3c_hsotg_init_fifo() to ensure that
the FIFO layout is correct and that the FIFOs are flushed before
acknowledging the reset.
Signed-off-by: Ben Dooks
---
drivers/usb/gadget/s3c-hsotg.c | 13 +
If there is more data in the request than we could fit into a single
hardware request, then check when the OutDone event is received if
we have more data, and if so, schedule the new data instead of trying
to complete the request (and in the case of EP0, sending a 0 packet
in the middle of a transf
Re-send of previous set, with corrected patches.
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Before trying a new setup transaction after getting an EP0 in complete
interrupt, check that the driver did not try and send more EP0 IN data
before enqueing a new setup transaction.
This fixes a bug where we cannot send all of the IN data in one go
so split the transfer, but then fail to send all
In shared fifo mode (used on older SoCs) the periodic in fifo beahves
much more like a packet buffer, discarding old data when writing new
data. Avoid this by ensuring that we do not load new transactions in
when there is data sitting already in the FIFO.
Note, this may not be an observed bug, we
The EP0 out limit is the same as the IN limit, so make them the same.
Signed-off-by: Ben Dooks
---
drivers/usb/gadget/s3c-hsotg.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 1020006..552ec89 1006
Up the FIFO size for the TX to 1024 entries, as this now seems to work
with all the cores. This fixes a problem when using large packets on
a core with MPS set to 512 can hang due to insufficient space for the
writes.
The hang arises due to getting the non-periodic FIFO empty IRQ but
not being abl
On Wed, Jul 07, 2010 at 08:27:53AM +0900, Kukjin Kim wrote:
> Russell King wrote:
> > What is the spacing of chunks of memory, and minimum alignment of those
> > chunks in physical address space?
>
> Some S5PC110(MCP D-type) has only available 80MiB in a bank.
> So the space accounts for 432MiB in
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