Hello,
On 12/17/2010 08:43 AM, Hyunwoong Kim wrote:
> The main scaler has four SFRs for main scaler ratio depends on FIMC version.
> FIMC 4.x has only two SFRs and FIMC 5.x has four SFRs for main scaler.
> Those are MainHorRatio, MainHorRatio_ext, MainVerRatio and MainverRatio_ext.
>
> The FIMC 5
On Fri, Dec 17, 2010 at 4:43 PM, Hyunwoong Kim wrote:
> The main scaler has four SFRs for main scaler ratio depends on FIMC version.
> FIMC 4.x has only two SFRs and FIMC 5.x has four SFRs for main scaler.
> Those are MainHorRatio, MainHorRatio_ext, MainVerRatio and MainverRatio_ext.
>
> The FIMC
In d7e81c2 (clocksource: Add clocksource_register_hz/khz interface) new
interfaces were added which simplify (and optimize) the selection of the
divisor shift/mult constants. Switch over to using this new interface.
Acked-by: Kukjin Kim
Signed-off-by: Russell King
---
arch/arm/mach-s5pv310/tim
Here is the entire set of clocksource and sched_clock patches which
have been previously posted. There's a couple of small tweaks in a
few of the patches (such as adding notrace to OMAP clocksource read
functions), and this also shows the proper ordering of these patches.
Still looking for acks o
From: SangWook Ju
This patch adds support CPUFREQ driver for S5PV310 and S5PC210. This can
support DVFS(Dynamic Voltage and Frequency Scaling). The voltage scaling
depends on existence of regulator.
Signed-off-by: Sangwook Ju
Signed-off-by: Sangbeom Kim
---
arch/arm/mach-s5pv310/cpufreq.c |
This patch adds support CPUFREQ driver for S5PV310 and S5PC210.
Changes since V1:
- All level of ARMCLK use APLL only.
- During PLL change(lock time), MPLL is used for temporary CPU source clock
[PATCH V2 1/3] ARM: S5PV310: Update CMU registers for CUPFREQ
[PATCH V2 2/3] ARM: S5PV310: Add support
From: SangWook Ju
This patch adds ARCH_HAS_CPUFREQ in Kconfig of ARCH_S5PV310 and updates
Makefile for supporting build S5PV310 CPUFREQ driver
Signed-off-by: Sangwook Ju
Signed-off-by: Sangbeom Kim
---
arch/arm/mach-s5pv310/Kconfig |1 +
arch/arm/mach-s5pv310/Makefile |1 +
2 files c
From: SangWook Ju
This patch adds CMU(Clock Management Unit) registers for S5PV310/S5PC210
CPUFREQ driver and modifies some register names according to datasheet.
Signed-off-by: Sangwook Ju
Signed-off-by: Sangbeom Kim
---
arch/arm/mach-s5pv310/clock.c | 10 ++--
arch/arm/m
This patch adds support for runtime pm using the functions.
- pm_runtime_get_sync()
- pm_runtime_put_sync()
pm_runtime_get_sync() and pm_runtime_put_sync() are called when
open or release function of framebufer driver is called to inform
the system if hardware is idle or not.
Signed-off-by: Jin
The main scaler has four SFRs for main scaler ratio depends on FIMC version.
FIMC 4.x has only two SFRs and FIMC 5.x has four SFRs for main scaler.
Those are MainHorRatio, MainHorRatio_ext, MainVerRatio and MainverRatio_ext.
The FIMC 5.x has 15 bit resolution for scaling ratio as below.
{MainHorRa
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