Hi,
At the moment perhaps the strongest argument for why this particular
arbitration scheme is needed is that's what the EC (embedded
controller) on the ARM Chromebook uses. There have been several
arguments in-house about whether this was the most ideal way to
structure things, but
Hi Tomasz,
[...]
+Required properties:
+- compatible : should be one of following:
+samsung,s3c24xx-pwm-timer - for 16-bit timers present on S3C24xx
+samsung,s3c64xx-pwm-timer - for 32-bit timers present on S3C64xx
and newer +- reg: base address and size of register area
The header file plat/common-smdk.h is used only in mach-s3c24xx/,
so this patch moves it into mach-s3c24xx directory.
Signed-off-by: Kukjin Kim kgene@samsung.com
---
arch/arm/mach-s3c24xx/common-smdk.c|3 ++-
arch/arm/{plat-samsung/include/plat =
Heiko Stübner wrote:
The register definitions are only used in the driver itself.
This also removes the last dependency on plat/ includes from the
i2c driver.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/mach-s3c24xx/mach-rx1950.c |1 -
Kukjin Kim wrote:
Heiko Stübner wrote:
The register definitions are only used in the driver itself.
This also removes the last dependency on plat/ includes from the i2c
driver.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
arch/arm/mach-s3c24xx/mach-rx1950.c |
Thomas Abraham wrote:
The address S3C_VA_UART is a statically ioremapped address. The driver
should not be using this. Instead, the driver should setup a mapping
during probe.
Cc: Kukjin Kim kgene@samsung.com
Looks good to me:
Acked-by: Kukjin Kim kgene@samsung.com
Greg, if
Sachin Kamat wrote:
Add 'default' case to silence the following warning:
arch/arm/plat-samsung/include/plat/sdhci.h:356:9: warning: switch with no
cases
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/plat-samsung/include/plat/sdhci.h |2 ++
1 files changed, 2
Tomasz Figa wrote:
On Monday 11 of February 2013 05:21:13 Shirish S wrote:
This patch corrects the pin function value of sd4_bus8 from 3
to 4.
This is verified on origen board for testing eMMC on
dw_mci controller.
Signed-off-by: Shirish S s.shir...@samsung.com
Signed-off-by: Alim
Jingoo Han wrote:
Use AUXDATA to set the device names for DP controller instance
discovered from device tree.
Signed-off-by: Ajay Kumar ajaykumar...@samsung.com
Signed-off-by: Jingoo Han jg1@samsung.com
---
Tested with SMDK5250 board
Changes since v2:
- rebase on linux-samsung
Heiko Stübner wrote:
This series finishes the irq rework by moving the irqs for s3c2412, s3c2440
and s3c2442 into the new structure.
Now the only open point is the different handling of the eint0 to eint3
interrupts on the s3c2412. On this SoC these interrupts are represented
in both the
Inderpal Singh wrote:
Only exynos4 based platforms have l2x0 cache controller. Hence check
the same before restoring the cache in resume.
I think, the code can determine by checking ARM main ID cp15 register
instead of Chip ID. Because if so, we don't need to do something for ahother
EXYNOS4
plat-samsung/irq.h did only contain functions for handling the spread out
subirqs on s3c24xx arches, which are not needed anymore.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Sorry for bringing this separate submission, but I just remembered
it this evening.
This applies on top of all the
From: Rob Herring rob.herr...@calxeda.com
Exynos boot is broken with commit 0529e315 (ARM: use common irqchip_init
for GIC init). This commit split the irqchip initialization into 2 calls
to of_irq_init. This does not work because of_irq_init requires interrupt
parents to be in the match list.
On 02/11/2013 10:50 PM, Stephen Warren wrote:
On 02/09/2013 03:29 PM, Sylwester Nawrocki wrote:
On 02/09/2013 01:32 AM, Stephen Warren wrote:
On 02/08/2013 05:05 PM, Sylwester Nawrocki wrote:
On 02/09/2013 12:21 AM, Stephen Warren wrote:
On 02/08/2013 04:16 PM, Sylwester Nawrocki wrote:
On
On Tue, Feb 12, 2013 at 04:04:52PM -0600, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
Exynos boot is broken with commit 0529e315 (ARM: use common irqchip_init
for GIC init). This commit split the irqchip initialization into 2 calls
to of_irq_init. This does not work because
Hi Arnd and Olof,
Here is Samsung fixes for v3.9 and it is not a critical fixes.
Please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
next/fixes-samsung
Thanks.
- Kukjin
The following changes since commit 7d1f9aeff1ee4a20b1aeb377dd0f579fe9647619:
Linux
Hi Rafael,
Here is changes for Samsung exynos cpufreq for v3.9.
Almost of them are changing exynos stuff in drivers/cpufreq, so should be
fine for cpufreq tree.
Please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git
next/cpufreq-exynos
If any problems, please
Hi James,
look like these patches are fine. Can you please integrate these
patches in your tree.
On Tue, Feb 5, 2013 at 10:17 PM, vinholika...@gmail.com wrote:
From: Vinayak Holikatti vinholika...@gmail.com
This patch set adds following features
- Seggregate PCI specific code in ufshcd.c
Adding Kukjin Kim who was accidentally missed out in the re-worked patches.
On Wed, Dec 5, 2012 at 8:51 AM, Abhilash Kesavan a.kesa...@samsung.com wrote:
The exynos5250 based chromebooks have a max77686 pmic on i2c channel 0.
Add support for the pmic in the common cros5250 dts file.
Tested
Hi Vinod,
On Tue, Feb 12, 2013 at 8:19 PM, Vinod Koul vinod.k...@intel.com wrote:
On Mon, Feb 11, 2013 at 02:08:20PM +0530, Padmavathi Venna wrote:
This looks fine, I have only question. The code seems to assume that pl330 dma
controller always uses DT. But I dont see that as dependency for
Hi Kukjin,
Thanks for reviewing the patch.
On 13 February 2013 00:57, Kukjin Kim kgene@samsung.com wrote:
Inderpal Singh wrote:
Only exynos4 based platforms have l2x0 cache controller. Hence check
the same before restoring the cache in resume.
I think, the code can determine by
Kukjin Kim wrote:
Heiko Stübner wrote:
plat-samsung/irq.h did only contain functions for handling the spread
out subirqs on s3c24xx arches, which are not needed anymore.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Sorry for bringing this separate submission, but I just
commit 7b45ed96 (ARM: S3C24XX: handle s3c2412 eints using new
infrastructure) introduced build warning and this patch fixes
that:
drivers/gpio/gpio-samsung.c: In function 's3c24xx_gpiolib_fbank_to_irq':
drivers/gpio/gpio-samsung.c:1126:5: warning: suggest explicit braces to avoid
ambiguous
Abhilash Kesavan wrote:
The exynos5250 based chromebooks have a max77686 pmic on i2c channel 0.
Add support for the pmic in the common cros5250 dts file.
Tested after enabling cpufreq support for exynos5250 SoC and varying the
arm frequency/voltage using the userspace governer.
Sangsu Park wrote:
Audio Subsystem has own clocks for I2S0 and PCM0 in all EXYNOS series.
This patch add clocks for I2S0 and PCM0 I/F.
Signed-off-by: Sangsu Park sangsu4u.p...@samsung.com
---
arch/arm/mach-exynos/Makefile |1 +
arch/arm/mach-exynos/clock-audss.c | 68
KyongHo Cho wrote:
On Fri, Feb 1, 2013 at 10:51 PM, Joerg Roedel j...@8bytes.org wrote:
Cho,
On Wed, Jan 02, 2013 at 02:53:49PM +0900, KyongHo Cho wrote:
On Tuesday, January 1, 2013, Sylwester Nawrocki
sylvester.nawro...@gmail.com
Cc: devicetree-disc...@lists.ozlabs.org
Since
Vivek Gautam wrote:
Based on 'usb-next'
Changes from v4:
- Modifying function names and driver names to follow a common
naming convention.
usb2phy for samsung-usb2phy driver
usb3phy for samsung-usb3phy driver
- Changing file names samsung-usb2.c to samsung-usb2phy.c
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