On 03/18/2013 06:34 PM, Heiko Stübner wrote:
> Am Montag, 18. März 2013, 23:14:52 schrieb Rob Herring:
>> On 03/18/2013 11:53 AM, Heiko Stübner wrote:
>>> Hi Rob,
>>>
>>> Am Montag, 18. März 2013, 16:54:03 schrieb Rob Herring:
On 03/17/2013 08:09 AM, Heiko Stübner wrote:
> The s3c2450 is s
Am Montag, 18. März 2013, 23:14:52 schrieb Rob Herring:
> On 03/18/2013 11:53 AM, Heiko Stübner wrote:
> > Hi Rob,
> >
> > Am Montag, 18. März 2013, 16:54:03 schrieb Rob Herring:
> >> On 03/17/2013 08:09 AM, Heiko Stübner wrote:
> >>> The s3c2450 is special in that it shares the cpu identification
On 03/18/2013 04:27 PM, Rob Herring wrote:
> On 03/18/2013 01:11 PM, Stephen Warren wrote:
>> On 03/18/2013 09:50 AM, Rob Herring wrote:
>>> On 03/13/2013 05:42 PM, Sylwester Nawrocki wrote:
Rob,
On 03/13/2013 03:39 PM, Rob Herring wrote:
> I fail to see what the hack is. The ord
On Monday 18 March 2013 17:27:35 Rob Herring wrote:
>
> I think it depends on the specific name the property is tied too. For
> interrupt and reg properties which have a long history and convention,
> the order should be defined. IIRC, this was Grant's position too. For
> new bindings, perhaps we
On 03/18/2013 01:11 PM, Stephen Warren wrote:
> On 03/18/2013 09:50 AM, Rob Herring wrote:
>> On 03/13/2013 05:42 PM, Sylwester Nawrocki wrote:
>>> Rob,
>>>
>>> On 03/13/2013 03:39 PM, Rob Herring wrote:
I fail to see what the hack is. The order of interrupt properties must
be defined by
On Monday 18 March 2013 17:14:52 Rob Herring wrote:
>
> > + s3c24xx,irqlist = <2 0 /* 2D */
> > +2 0 /* IIC1 */
> > +0 0 /* reserved */
> > +0 0 /* reserved */
> > +
On 03/18/2013 11:53 AM, Heiko Stübner wrote:
> Hi Rob,
>
> Am Montag, 18. März 2013, 16:54:03 schrieb Rob Herring:
>> On 03/17/2013 08:09 AM, Heiko Stübner wrote:
>>> The s3c2450 is special in that it shares the cpu identification with the
>>> s3c2416 but provides more interrupts for its additiona
Certain pin control registers can be accessed from different contexts,
i.e. pinctrl, gpio and irq functions. This makes the locking provided by
pin control core insufficient.
This patch adds necessary locking using a per bank spinlock as it was
done in the old Samsung GPIO driver.
Signed-off-by:
On Monday 18 of March 2013 22:31:51 Tomasz Figa wrote:
> Since pinctrl-samsung is a common part of the pin control support for
> several Samsung SoCs, it can be compiled without Exynos support enabled.
>
> This patch surrounds Exynos-specific driver data with ifdefs to include
> them only when sup
Since pinctrl-samsung is a common part of the pin control support for
several Samsung SoCs, it can be compiled without Exynos support enabled.
This patch surrounds Exynos-specific driver data with ifdefs to include
them only when support for Exynos is enabled.
Signed-off-by: Tomasz Figa
---
dri
This patch splits pin bank description into two structures, one
describing bank type (currently only bitfield widths), which can be
shared across multiple banks and second containing bank-specific
parameters including a pointer to a bank type struct.
It is a prerequisite for further patch removing
This patch replaces statically hardcoded register offsets of Exynos SoCs
with an array of register offsets in samsung_pin_bank_type struct.
Thanks to this change, support for SoCs with other set and order of
registers can be added (e.g. S3C24xx and S3C64xx).
Signed-off-by: Tomasz Figa
---
drive
This patch adds pinctrl-s3c64xx driver which implements pin control
interface for Samsung S3C64xx SoCs.
Signed-off-by: Tomasz Figa
---
.../bindings/pinctrl/samsung-pinctrl.txt | 3 +
drivers/pinctrl/Kconfig| 5 +
drivers/pinctrl/Makefile
This patch adds support for banks that have more than one function
configuration registers, e.g. some of the banks of S3C64xx SoCs.
Signed-off-by: Tomasz Figa
---
drivers/pinctrl/pinctrl-samsung.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-samsung.c
This series makes necessary preparations to add support for pin controller
available on Samsung S3C64xx using pinctrl-samsung driver and then adds
pinctrl-s3c64xx driver which implements SoC-specific part of the code.
It has been tested on a tiny6410 (mini6410-compatible) board with my patches
for
From: Guennadi Liakhovetski
Add a V4L2 OF parser, implementing bindings documented in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Signed-off-by: Guennadi Liakhovetski
[s.nawro...@samsung.com: various corrections and improvements
since the initial version]
Signed-off-by: Sylwes
On 03/17/2013 08:07 AM, Heiko Stübner wrote:
> Add the necessary code to initialize the interrupt controller
> thru devicetree data using the irqchip infrastructure.
>
> On dt machines the eint-type interrupts in the main interrupt controller
> get mapped as regular edge-types, as their wakeup and
On 03/18/2013 09:50 AM, Rob Herring wrote:
> On 03/13/2013 05:42 PM, Sylwester Nawrocki wrote:
>> Rob,
>>
>> On 03/13/2013 03:39 PM, Rob Herring wrote:
>>> I fail to see what the hack is. The order of interrupt properties must
>>> be defined by the binding. interrupt-names is auxiliary data and mus
Hi Rob,
Am Montag, 18. März 2013, 16:54:03 schrieb Rob Herring:
> On 03/17/2013 08:09 AM, Heiko Stübner wrote:
> > The s3c2450 is special in that it shares the cpu identification with the
> > s3c2416 but provides more interrupts for its additional components.
> >
> > It also shares the layout of
On 03/17/2013 08:09 AM, Heiko Stübner wrote:
> The s3c2450 is special in that it shares the cpu identification with the
> s3c2416 but provides more interrupts for its additional components.
>
> It also shares the layout of the main interrupt register with the s3c2443
> and therefore reuses this de
On 03/13/2013 05:42 PM, Sylwester Nawrocki wrote:
> Rob,
>
> On 03/13/2013 03:39 PM, Rob Herring wrote:
>> I fail to see what the hack is. The order of interrupt properties must
>> be defined by the binding. interrupt-names is auxiliary data and must
>> not be required by an OS.
>
> It is clear t
On Sun March 17 2013 22:03:38 Sylwester Nawrocki wrote:
> On 03/12/2013 03:44 PM, Hans Verkuil wrote:
> > On Mon 11 March 2013 20:44:49 Sylwester Nawrocki wrote:
> [...]
> >> +static int isp_video_capture_open(struct file *file)
> >> +{
> >> + struct fimc_isp *isp = video_drvdata(file);
> >> + in
Hi Viresh,
On Tue, Mar 12, 2013 at 4:19 PM, Viresh Kumar wrote:
> This is what Russell told me a long time back:
> "Don't use Adding, Fixing, etc words as this work is not something, which is
> already done."
>
> So your subject should have been: "cpufreq: exynos: Add cpufreq driver
> for exynos5
Hello,
On Mon, Mar 18, 2013 at 03:48:24PM +0530, Thomas Abraham wrote:
> On 18 March 2013 14:12, Shawn Guo wrote:
> > On Sat, Mar 16, 2013 at 06:20:01PM +0530, Thomas Abraham wrote:
> >> The mxs platform specific clk-div clock is an extended version of the
> >> basic integer divider clock type th
On 18 March 2013 14:12, Shawn Guo wrote:
> On Sat, Mar 16, 2013 at 06:20:01PM +0530, Thomas Abraham wrote:
>> The mxs platform specific clk-div clock is an extended version of the
>> basic integer divider clock type that supports checking the stability
>> status of the divider clock output. This t
Hi Shaik,
On 03/15/2013 10:00 AM, Shaik Ameer Basha wrote:
> On Thu, Mar 7, 2013 at 9:05 PM, Sylwester Nawrocki
> wrote:
...
>> May I ask what do you need this for ? This code won't be used for
>> Exynos4 and Exynos5 SoCs starting from 3.10. And it is going to be
>> removed once other platforms a
On Sat, Mar 16, 2013 at 06:20:01PM +0530, Thomas Abraham wrote:
> The mxs platform specific clk-div clock is an extended version of the
> basic integer divider clock type that supports checking the stability
> status of the divider clock output. This type of clock is found on
> some of the Samsung
27 matches
Mail list logo
