Please apply this. It's way overdue. It fixes customer kernel crashes
we've seen in the field.
I'd also advocate for seeing this be applied to stable kernels.
thanks,
grant
On Thu, Mar 13, 2014 at 10:02 PM, Cho KyongHo wrote:
> This commit adds cache flush for removed small and large page entr
Tomasz Figa writes:
> This patch introduces generic code to perform power domain look-up using
> device tree and automatically bind devices to their power domains.
> Generic device tree binding is introduced to specify power domains of
> devices in their device tree nodes.
>
> Backwards compatibi
Hi Chanwoo,
On 13.03.2014 09:17, Chanwoo Choi wrote:
This patchset support devicetree and use common ppmu driver instead of
individual code of exynos4_bus.c to remove duplicate code. Also this patchset
get the resources for busfreq from dt data by using DT helper function.
- PPMU register addres
Hi Chanwoo,
On 13.03.2014 09:17, Chanwoo Choi wrote:
This patch disable ppmu clocks before entering suspend state to remove
power-leakage and enable ppmu clocks on resume function.
I don't think there is any need for this, because all the clocks are
stopped anyway in SLEEP mode.
Best regard
Hi Chanwoo,
On 13.03.2014 09:17, Chanwoo Choi wrote:
This patch fix bug about resource leak when happening probe fail and code clean
to add debug message.
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/exynos/exynos4_bus.c | 32 ++--
1 file changed, 26 insertion
Hi Chanwoo,
On 13.03.2014 09:17, Chanwoo Choi wrote:
There are not the clock controller of ppmudmc0/1. This patch control the clock
of ppmudmc0/1 which is used for monitoring memory bus utilization.
Also, this patch code clean about regulator control and free resource
when calling exit/remove f
Hi Chanwoo, Mark,
On 14.03.2014 11:56, Chanwoo Choi wrote:
Hi Mark,
On 03/14/2014 07:35 PM, Mark Rutland wrote:
On Fri, Mar 14, 2014 at 07:14:37AM +, Chanwoo Choi wrote:
Hi Mark,
On 03/14/2014 02:53 AM, Mark Rutland wrote:
On Thu, Mar 13, 2014 at 08:17:29AM +, Chanwoo Choi wrote:
T
Hi Robert,
On 14.03.2014 11:13, Robert Baldyga wrote:
This patch adds device tree node for IRQ used by max8997.
Generally, this patch does not add just a node, but rather "IRQ line
specification for the MAX8997 PMIC chip and necessary pinctrl group to
configure pull-up and driver strength o
Hi KyongHo,
On 14 March 2014 19:13, Tomasz Figa wrote:
> Hi KyongHo,
>
>
> On 14.03.2014 06:09, Cho KyongHo wrote:
>>
>> exynos-iommu driver must care about master H/W's gate clock as well as
>> System MMU's gate clock. To enhance readability of the source code,
>> macros to gate/ungate those cl
Hi KyongHo,
On 14.03.2014 06:10, Cho KyongHo wrote:
Some master device descriptor like fimc-is which is an abstraction
of very complex H/W may have multiple System MMUs. For those devices,
the design of the link between System MMU and its master H/W is needed
to be reconsidered.
A link structur
Hi KyongHo,
On 14.03.2014 06:10, Cho KyongHo wrote:
This adds support for Suspend to RAM and Runtime Power Management.
Since System MMU is located in the same local power domain of its
master H/W, System MMU must be initialized before it is working if
its power domain was ever turned off. TLB i
Hi KyongHo,
On 14 March 2014 10:39, Cho KyongHo wrote:
> This commit adds device tree support for System MMU.
>
> Signed-off-by: Cho KyongHo
> ---
> drivers/iommu/Kconfig|5 ++---
> drivers/iommu/exynos-iommu.c | 21 +
> 2 files changed, 19 insertions(+), 7 del
Hi KyongHo,
On 14 March 2014 10:35, Cho KyongHo wrote:
> This patch uses managed device helper functions in the probe().
>
> Signed-off-by: Cho KyongHo
> ---
[snip]
> + data->clk = devm_clk_get(dev, "sysmmu");
> + if (IS_ERR(data->clk)) {
> + dev_info(dev, "No gate clo
Hi KyongHo,
On 14.03.2014 06:09, Cho KyongHo wrote:
exynos-iommu driver must care about master H/W's gate clock as well as
System MMU's gate clock. To enhance readability of the source code,
macros to gate/ungate those clocks are defined.
Signed-off-by: Cho KyongHo
---
drivers/iommu/exynos-i
Hi KyongHo,
On 14.03.2014 06:09, Cho KyongHo wrote:
This commit adds device tree support for System MMU.
Signed-off-by: Cho KyongHo
---
drivers/iommu/Kconfig|5 ++---
drivers/iommu/exynos-iommu.c | 21 +
2 files changed, 19 insertions(+), 7 deletions(-)
d
On Thu, Mar 13, 2014 at 10:40:05AM -0700, Tim Harvey wrote:
> The invalid value of #address-cells in the imx6 pcie host controller node
> causes of_irq_parse_raw() to incorrectly advance through an interrupt-map
> table of more than one interrupt.
>
> This patch resolves this issue and allows prop
Hi KyongHo,
On 14.03.2014 06:05, Cho KyongHo wrote:
This patch uses managed device helper functions in the probe().
Signed-off-by: Cho KyongHo
---
drivers/iommu/exynos-iommu.c | 64 +-
1 file changed, 26 insertions(+), 38 deletions(-)
diff --git a/
Hi KyongHo,
On 14.03.2014 06:05, Cho KyongHo wrote:
System MMU driver is changed to control only a single instance of
System MMU at a time. Since a single instance of System MMU has only
a single clock descriptor for its clock gating, there is no need to
obtain two or more clock descriptors.
On Thu, Mar 13, 2014 at 6:25 PM, Jason Gunthorpe
wrote:
> On Thu, Mar 13, 2014 at 11:44:33AM -0600, Stephen Warren wrote:
>> On 03/13/2014 11:40 AM, Tim Harvey wrote:
>> > When using interrupt-maps, the size of a map entry is #address-cells +
>> > #interrupt-cells for the parent interrupt control
Register APLL rate table in Exynos5420 clock driver.
Will be required for the CPUFreq driver.
Signed-off-by: Sachin Kamat
---
drivers/clk/samsung/clk-exynos5420.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/c
Hi KyongHo,
On 14.03.2014 06:08, Cho KyongHo wrote:
Runtime power management by exynos-iommu driver independently from
master H/W's runtime pm is not useful for power saving since attaching
master H/W in probing time turns on its local power endlessly.
Thus this removes runtime pm API calls.
Run
On Thu, Mar 13, 2014 at 10:33:29AM +, Mark Rutland wrote:
> On Wed, Mar 12, 2014 at 04:31:56AM +, Kukjin Kim wrote:
> > > > +/ {
> > > > + model = "SAMSUNG SSDK-GH7 board based on GH7 SoC";
> > > Is the "based on GH7 SoC" part necessary? Does the "SSDK-GH7" not give
> > > that away?
Hi KyongHo,
On 14.03.2014 06:06, Cho KyongHo wrote:
This patch adds dts entries for the System MMU devices found on
Exynos4 and Exynos5 SoC series and the System MMU binding
documentation.
CC: Rob Herring
CC: Sylwester Nawrocki
Signed-off-by: Cho KyongHo
---
.../bindings/iommu/samsung,exyn
Hi KyongHo,
On 14.03.2014 06:06, Cho KyongHo wrote:
This adds gate clocks of all System MMUs and their master IPs
that are not apeared in clk-exynos5250.c and clk-exynos5420.c
Also fixes GATE_IP_ACP to 0x18800 and changed GATE_DA to GATE
for System MMU clocks in clk-exynos4.c
Signed-off-by: Cho
On Thu, Mar 13, 2014 at 03:25:50PM -0700, Tim Harvey wrote:
> On Thu, Mar 13, 2014 at 11:25 AM, Jason Gunthorpe
> wrote:
> > On Thu, Mar 13, 2014 at 11:44:33AM -0600, Stephen Warren wrote:
> >> On 03/13/2014 11:40 AM, Tim Harvey wrote:
> >> > When using interrupt-maps, the size of a map entry is #
On 14 March 2014 17:19, Cho KyongHo wrote:
>> From: Sachin Kamat [mailto:sachin.ka...@linaro.org]
>> Sent: Friday, March 14, 2014 7:00 PM
>>
>> On 14 March 2014 10:31, Cho KyongHo wrote:
>> > Commit 25e9d28d92 (ARM: EXYNOS: remove system mmu initialization from
>> > exynos tree) removed arch/arm/
> From: Sachin Kamat [mailto:sachin.ka...@linaro.org]
> Sent: Friday, March 14, 2014 7:00 PM
>
> On 14 March 2014 10:31, Cho KyongHo wrote:
> > Commit 25e9d28d92 (ARM: EXYNOS: remove system mmu initialization from
> > exynos tree) removed arch/arm/mach-exynos/mach/sysmmu.h header without
> > remo
Hi Mark,
On 03/14/2014 07:35 PM, Mark Rutland wrote:
> On Fri, Mar 14, 2014 at 07:14:37AM +, Chanwoo Choi wrote:
>> Hi Mark,
>>
>> On 03/14/2014 02:53 AM, Mark Rutland wrote:
>>> On Thu, Mar 13, 2014 at 08:17:29AM +, Chanwoo Choi wrote:
This patch add busfreq driver for Exynos4210/Exy
On Friday, March 14, 2014 12:14:03 PM Chanwoo Choi wrote:
> Hi,
>
> On 03/14/2014 01:43 AM, Bartlomiej Zolnierkiewicz wrote:
> >
> > Hi,
> >
> > On Thursday, March 13, 2014 05:17:21 PM Chanwoo Choi wrote:
> >> This patchset support devicetree and use common ppmu driver instead of
> >> individual
On Fri, Mar 14, 2014 at 07:14:37AM +, Chanwoo Choi wrote:
> Hi Mark,
>
> On 03/14/2014 02:53 AM, Mark Rutland wrote:
> > On Thu, Mar 13, 2014 at 08:17:29AM +, Chanwoo Choi wrote:
> >> This patch add busfreq driver for Exynos4210/Exynos4x12 memory interface
> >> and bus to support DVFS(Dyna
This patch adds device tree node for IRQ used by max8997.
Signed-off-by: Robert Baldyga
---
arch/arm/boot/dts/exynos4210-trats.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index 1d18428..
On 14 March 2014 10:31, Cho KyongHo wrote:
> Commit 25e9d28d92 (ARM: EXYNOS: remove system mmu initialization from
> exynos tree) removed arch/arm/mach-exynos/mach/sysmmu.h header without
> removing remaining use of it from exynos-iommu driver, thus causing a
> compilation error.
>
> This patch fi
This patch disable ppmu clocks before entering suspend state to remove
power-leakage and enable ppmu clocks on resume function.
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/exynos/exynos4_bus.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drive
This patchset support devicetree and use common ppmu driver instead of
individual code of exynos4_bus.c to remove duplicate code. Also this patchset
get the resources for busfreq from dt data by using DT helper function.
- PPMU register address
- PPMU clock
- Regulator for INT/MIF block
This patch
This patch use SET_SYSTEM_SLEEP_PM_OPS macro instead of legacy method.
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/exynos/exynos4_bus.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/devfreq/exynos/exynos4_bus.c
b/drivers/devfreq/exynos/exynos4_bus.c
index 60
This patch fix bug about resource leak when happening probe fail and code clean
to add debug message.
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/exynos/exynos4_bus.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/devfreq/exynos/ex
There are not the clock controller of ppmudmc0/1. This patch control the clock
of ppmudmc0/1 which is used for monitoring memory bus utilization.
Also, this patch code clean about regulator control and free resource
when calling exit/remove function.
For example,
busfreq@106A {
compat
This patch use common ppmu driver of exynos_ppmu.c driver instead of individual
function related to PPC because PPMU is integrated module with both PPC and
Bus event generator. When using PPMU to get bus performance read/write event,
exynos4_bus.c don't need to consider memory type.
And get ppmu a
This patch add CONFIG_PM_OPP dependecy to exynos4_bus driver
to fix probe fail as following log:
[3.721389] exynos4-busfreq busfreq.3: Fail to add opp entries.
[3.721697] exynos4-busfreq: probe of busfreq.3 failed with error -22
If CONFIG_PM_OPP is disabled, dev_pm_opp_find_freq_floor() i
This patch introduce device tree binding for the Exynos4's busfreq driver.
The Exynos4's busfreq driver support DVFS(Dynamic Voltage Frequency Scaling)
of Exynos4 memory bus to optimize power-consumption on runtime state.
Exynos4's busfreq driver need the utilization of memory bus. So, busfreq driv
This patch support DT(DeviceTree) method to probe exynos4_bus and get device
id of each Exynos4 SoC by using dt helper function.
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/exynos/exynos4_bus.c | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/dri
Hi,
We are trying to enable the UART3 on COM18 pins of arndale board. The UART3 RXD
and TXD are on pins 2 and 4 which as per the base board specification is
connected as
XuRXD3 : UART_3_RXD/GPA1[4] : 2
XuTXD3 : UART_3_TXD/GPA1[5] : 4
As per the public reference manual of exynos 5250, there is
Hi Mark,
On 03/14/2014 02:53 AM, Mark Rutland wrote:
> On Thu, Mar 13, 2014 at 08:17:29AM +, Chanwoo Choi wrote:
>> This patch add busfreq driver for Exynos4210/Exynos4x12 memory interface
>> and bus to support DVFS(Dynamic Voltage Frequency Scaling) according to PPMU
>> counters. PPMU (Perfor
43 matches
Mail list logo
