Hi Joonyoung,
On 04/17/2014 03:54 AM, Joonyoung Shim wrote:
Hi Tomasz,
On 04/17/2014 12:12 AM, Tomasz Stanislawski wrote:
This patch continues shift of DRM EXYNOS to DT-only configuration.
The usage of the old structure for HDMI's platform data is
removed.
Signed-off-by: Tomasz
Hi Tomasz,
On 04/16/2014 11:28 PM, Tomasz Figa wrote:
Hi Chanwoo,
On 15.04.2014 03:59, Chanwoo Choi wrote:
This patch fix the offset of CPU boot address and don't operate smc call
of SMC_CMD_CPU1BOOT command for Exynos3250.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by:
The rtc-s5m driver does not support all of S2M and S5M chipsets
supported by main MFD sec-core driver. For such chipsets unsupported by
rtc-s5m, the MFD sec-core driver initialized regmap with default config.
This config in such cases wouldn't work at all.
The main MFD sec-core driver
(restoring the Cc list I cleared accidentally in previous reply)
On 16/04/14 21:29, Rob Herring wrote:
On Wed, Apr 16, 2014 at 12:19 PM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
On 16/04/14 17:34, Rob Herring wrote:
On Tue, Apr 15, 2014 at 12:34 PM, Sylwester Nawrocki
Hi Tushar,
On 04/15/2014 02:09 PM, Tushar Behera wrote:
On 15 April 2014 07:29, Chanwoo Choi cw00.c...@samsung.com wrote:
This patch fix the offset of CPU boot address and don't operate smc call
of SMC_CMD_CPU1BOOT command for Exynos3250.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Nearly all of the registers in tps65090 combine control bits and
status bits. Turn off caching of all registers except the select few
that can be cached.
In order to avoid adding more duplicate #defines, we also move some
register offset definitions to the mfd driver (and resolve
Hi,
The patchset presents alternative approach to superdevice DT node
and components framework. It also refactors Exynos DRM device initialization.
The first patch uses linker sections to get rid of ifdef macros, it is not
essential for the rest of patchset but it makes code more readable.
The patch removes driver registration code based on preprocessor conditionals.
Instead it uses private linker section to create array of drm drivers.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
v2:
- minor fixes of compilation issues
---
drivers/gpu/drm/exynos/Makefile | 2
exynos_drm is composed from multiple devices which provides different
interfaces. To properly start/stop drm master device it should track
readiness of all its components. This patch uses pending_components
framework to perform this task.
On module initialization before component driver
Many subsystems (eg. DRM, ALSA) requires that multiple devices should
be composed into one superdevice. The superdevice cannot start until
all components are ready and it should stop before any of its components
becomes not-ready.
This framework provides a way to track readiness of all components
Hi Tomasz,
On 04/16/2014 08:49 PM, Tomasz Figa wrote:
Hi Chanwoo,
On 16.04.2014 12:11, Chanwoo Choi wrote:
This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
Cc: Rob Herring
In case of using CPU interface panel, the relevant registers should be set.
So this patch adds relevant dt bindings.
Changelog v2:
- Changes samsung,sysreg-phandle to samsung,sysreg
Signed-off-by: YoungJun Cho yj44@samsung.com
Signed-off-by: Inki Dae inki@samsung.com
Signed-off-by:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings, delays
and physical size.
Changelog v2:
- Adds unit address (commented by Sachin Kamat)
Changelog v3:
- Removes optional delay, size properties (commented by Laurent Pinchart)
- Adds OLED
This patch adds MIPI-DSI command mode based S6E3FA0 AMOLED LCD Panel driver.
Changelog v2:
- Declares delay, size properties in probe routine instead of DT
Signed-off-by: YoungJun Cho yj44@samsung.com
Signed-off-by: Inki Dae inki@samsung.com
Signed-off-by: Kyungmin Park
On Wed, Apr 16 2014 at 5:33:31 am BST, Jungseok Lee jays@samsung.com
wrote:
This patch adds 4 levels of translation tables implementation for both
HYP and stage2. A combination of 4KB + 4 levels host and 4KB + 4 levels
guest can run on ARMv8 architecture as introducing this feature.
Just
Lee,
On Thu, Apr 17, 2014 at 4:00 AM, Lee Jones lee.jo...@linaro.org wrote:
Nearly all of the registers in tps65090 combine control bits and
status bits. Turn off caching of all registers except the select few
that can be cached.
In order to avoid adding more duplicate #defines, we also
On Thu, 17 Apr 2014 09:08:47 +0100
Lee Jones lee.jo...@linaro.org wrote:
MFD changes look good to me. If Alessandro provides his Ack for the
RTC adaptions I can setup an MFD-RTC branch for him to pull from in
order to save conflicts at merge time.
Hello,
I do not keep an rtc git, so
From: David Hendricks dhend...@chromium.org
To avoid spamming the EC we calculate the time between the previous
transfer and the current transfer and force a delay if the time delta
is too small.
However, a small miscalculation causes the delay period to be
far too short. Most noticably this
The main transfer function for cros_ec_spi can be called by more than
one client at a time. Make sure that those clients don't stomp on
each other by locking the bus for the duration of the transfer
function.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec_spi.c | 26
We're adding i2c tunneling to the list of things that goes over
cros_ec. i2c tunneling can be slooow, so increase our deadline to
100ms to account for that.
Signed-off-by: Doug Anderson diand...@chromium.org
---
drivers/mfd/cros_ec_spi.c | 24
1 file changed, 16
This adds the EC i2c tunnel (and devices under it) to the
tegra124-venice2 device tree.
Signed-off-by: Doug Anderson diand...@chromium.org
---
arch/arm/boot/dts/tegra124-venice2.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git
The cros_ec_spi transfer had two problems with its timeout code:
1. It looked at the timeout even in the case that it found valid data.
2. If the cros_ec_spi code got switched out for a while, it's possible
it could get a timeout after a single loop. Let's be paranoid and
make sure we do
From: Bill Richardson wfric...@chromium.org
This just updates include/linux/mfd/cros_ec_commands.h to match the
latest EC version (which is the One True Source for such things). See
https://chromium.googlesource.com/chromiumos/platform/ec
[dianders: took today's ToT version from the Chromium OS
On ARM Chromebooks we have a few devices that are accessed by both the
AP (the main Application Processor) and the EC (the Embedded
Controller). These are:
* The battery (sbs-battery).
* The power management unit tps65090.
On the original Samsung ARM Chromebook these devices were on an I2C
bus
This series adds the most critical cros_ec changes for newer boards
using cros_ec. Specifically:
* Fixes timing/locking issues with the previously upstreamed (but
never used upstream) cros_ec_spi driver.
* Updates the cros_ec header file to the latest version which allows
us to use newer EC
On Thu, Apr 17, 2014 at 01:28:50PM +0200, Andrzej Hajda wrote:
+out:
+ if (ret != -EPROBE_DEFER)
+ exynos_drm_dev_ready(pdev-dev);
So we end up with everyone needing a ready call in each sub-driver
back into the main driver... this makes it impossible to write a
generic
On Thu, Apr 17, 2014 at 01:28:50PM +0200, Andrzej Hajda wrote:
+static int exynos_drm_add_blocker(struct device *dev, void *data)
+{
+ struct device_driver *drv = data;
+
+ if (!platform_bus_type.match(dev, drv))
+ return 0;
+
+ device_lock(dev);
+ if
This patchset support new Exynos3250 Samsung SoC based on Cortex-A7 dual core.
Exynos3250 is a System-On-Chip (SoC) that is based on 32-bit RISC processor
for Smartphone. It is desigend with the 28nm low-power high-K metal gate process
and provides the best performance features.
This patchset
This patch fix the offset of CPU boot address and don't need to send smc call
of SMC_CMD_CPU1BOOT command for secondary CPU boot because Exynos3250 removes
WFE in secure mode.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
This patch add Exynos3250's SoC ID. Exynos 3250 is System-On-Chip(SoC) that
is based on the 32-bit RISC processor for Smartphone. Exynos3250 uses Cortex-A7
dual cores and has a target speed of 1.0GHz.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park
This patch decide proper lowpower mode of either a15 or a9 according to own ID
from Main ID register.
Cc: Arnd Bergmann a...@arndb.de
Cc: Marc Zynigier marc.zyng...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
From: Kyungmin Park kyungmin.p...@samsung.com
This patch fix the offset of CPU boot address and change parameter of smc call
of SMC_CMD_CPU1BOOT command for Exynos4212.
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
From: Tomasz Figa t.f...@samsung.com
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7
using common clock framework. The CMU (Clock Management Unit) of Exynos3250
control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses,
and function clocks for individual
The Exynos3250 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree based
clock lookup and clkdev based clock lookups are supported.
Cc: Mike Turquette mturque...@linaro.org
Cc: Kukjin Kim kgene@samsung.com
Cc: Rob Herring
From: Tomasz Figa t.f...@samsung.com
This patch add new exynos3250.dtsi to support Exynos3250 SoC based on Cortex-A7
dual core and includes following dt nodes:
- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support
This patchset support cpufreq driver for Exynos3250 which uses the Cortex-A7
dual cores and has a target speed of 1.0 GHz and code clean using dev_err/info
instead of pr_err/info function.
This patchset has a dependency on following patchset[1] to support Exynos3250:
[1]
This patch uses dev_err/info function to show accurate log message with device
name
instead of pr_err/info function.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/cpufreq/exynos-cpufreq.c | 21 -
On Thursday, April 17, 2014 9:13 PM, Marc Zyngier wrote:
On Wed, Apr 16 2014 at 5:33:31 am BST, Jungseok Lee jays@samsung.com
wrote:
This patch adds 4 levels of translation tables implementation for both
HYP and stage2. A combination of 4KB + 4 levels host and 4KB + 4
levels guest
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