Hi,
It's also related with clock-gating.
Mainline kernel is using the "clkgate-delay = 0" by default.
If we use this value, Every request time should be gated/ungated...
Then it may be faced the race-condition...In my experiment, it occasionally
occurred the CRC error or other problem.
And it's a
On 2014년 07월 15일 02:22, Olof Johansson wrote:
> Inki,
>
> You have acks, and you have the tested-bys you requested. Can you
> please pick this up quickly so that we can have graphics working with
> an upstream kernel on chromebooks?
>
> Dave, if Inki keeps dragging his feet like this can you plea
Doug,
On Mon, Jul 14, 2014 at 10:30 PM, Doug Anderson wrote:
> Vikas,
>
> On Sun, Jul 13, 2014 at 11:33 PM, Vikas Sajjan
> wrote:
>> From: Doug Anderson
>>
>> The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
>> being reset across sleep/wake. If we don't set it to anything
On Tue, Jul 15, 2014 at 12:20 AM, Olof Johansson wrote:
> On Mon, Jul 14, 2014 at 9:47 AM, Doug Anderson wrote:
>> Sachin,
>>
>> On Wed, Jul 9, 2014 at 3:22 AM, Sachin Kamat
>> wrote:
> Gave this a go on my board farm as well, it looks better than before
> for sure. Boot logs are at:
> http:
Hi Doug,
On Mon, Jul 14, 2014 at 10:17 PM, Doug Anderson wrote:
> Sachin,
>
> On Wed, Jul 9, 2014 at 3:22 AM, Sachin Kamat wrote:
>> Removed outdated configs. Enabled most of the configs used on latest
>> Exynos based platforms. This will provide a reference for users trying
>> to verify and tes
Hello Mark,
On 15 July 2014 00:45, Mark Brown wrote:
> On Tue, Jul 15, 2014 at 12:31:32AM +0530, Naveen Krishna Ch wrote:
>
>> in this case spi-s3c64xx.c will continue to ignore the generic SPI "cs-gpios"
>> implementation.
>
>> I'm willing to implement any suggestion to fix this issue.
>
> The p
Hi Tomasz,
On Mon, Jul 14, 2014 at 7:08 PM, Thomas Abraham wrote:
> Changes since v6:
> - Fixes suggested by Amit Daniel .
>
> This patch series removes the use of Exynos4210 and Exynos5250 specific
> cpufreq
> drivers and enables the use of cpufreq-cpu0 driver for these platforms. This
> series
On Mon, Jul 14, 2014 at 9:04 PM, Sylwester Nawrocki
wrote:
> On 11/07/14 14:00, Tushar Behera wrote:
>> @@ -103,17 +140,11 @@ static int exynos_audss_clk_probe(struct
>> platform_device *pdev)
>> return PTR_ERR(reg_base);
>> }
>>
>> - clk_table = devm_kzalloc(&pdev->dev,
>
On 2014년 07월 14일 20:03, Thierry Reding wrote:
> On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote:
>> On 07/14/2014 06:41 PM, Thierry Reding wrote:
> [...]
>>> That said, I've been doing some research and it seems like we have a
>>> somewhat similar feature on Tegra. What happens there i
On Mon, Jul 14, 2014 at 6:28 PM, Kukjin Kim wrote:
> Olof Johansson wrote:
>>
>> On Mon, Jul 14, 2014 at 9:47 AM, Doug Anderson wrote:
>> > Sachin,
>> >
>> > On Wed, Jul 9, 2014 at 3:22 AM, Sachin Kamat
>> > wrote:
>> >> Removed outdated configs. Enabled most of the configs used on latest
>> >>
Olof Johansson wrote:
>
> On Mon, Jul 14, 2014 at 9:47 AM, Doug Anderson wrote:
> > Sachin,
> >
> > On Wed, Jul 9, 2014 at 3:22 AM, Sachin Kamat
> > wrote:
> >> Removed outdated configs. Enabled most of the configs used on latest
> >> Exynos based platforms. This will provide a reference for us
On Mon, Jul 14, 2014 at 09:38:59PM +0100, Joel Schopp wrote:
> I agree that these patches would be very useful. I just rebased my fix
> for a VTTBR_BADDR_MASK bug on one of these patches that could be pulled
> out independently. See
> https://lists.cs.columbia.edu/pipermail/kvmarm/2014-July/01048
This patch changes the fifo reset code to follow the reset procedure
outlined in the documentation of Synopsys Mobile storage host databook.
Signed-off-by: Sonny Rao
Signed-off-by: Yuvaraj Kumar C D
---
v2: Add Generic DMA support
per the documentation, move interrupt clear before wait
m
On Mon, 14 Jul 2014 14:14:24 -0400, Nicholas Krause said:
> This patch addresses the fix me message in this file that states to
> remove all definitions not related to reg-clocks in this header
> file.
>
> Signed-off-by: Nicholas Krause
> ---
> arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22
I agree that these patches would be very useful. I just rebased my fix
for a VTTBR_BADDR_MASK bug on one of these patches that could be pulled
out independently. See
https://lists.cs.columbia.edu/pipermail/kvmarm/2014-July/010480.html
The original author Jungseok Lee is no longer available to wo
On Mon, May 12, 2014 at 4:40 AM, Jungseok Lee wrote:
> This patch adds virtual address space size and a level of translation
> tables to kernel configuration. It facilicates introduction of
> different MMU options, such as 4KB + 4 levels, 16KB + 4 levels and
> 64KB + 3 levels, easily.
Is there a
To comment on the snow failures that I know about:
On Mon, Jul 14, 2014 at 11:50 AM, Olof Johansson wrote:
> [ERR] [2.118115] cros-ec-i2c-tunnel cros-ec-i2c-tunnel.2: Couldn't
> read remote-bus property
Known issue. The i2c-tunnel is not present on snow. This will be
fixed once we send up
On Tue, Jul 15, 2014 at 12:31:32AM +0530, Naveen Krishna Ch wrote:
> in this case spi-s3c64xx.c will continue to ignore the generic SPI "cs-gpios"
> implementation.
> I'm willing to implement any suggestion to fix this issue.
The problem isn't what you're trying to do, the problem is verifying
t
Hello Mark,
On 14 July 2014 22:55, Mark Brown wrote:
> On Mon, Jul 14, 2014 at 11:11:44AM +0530, Naveen Krishna Chatradhi wrote:
>
>> @@ -812,6 +800,10 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
>> spi->controller_data = cs;
>> }
>>
>> + /* For the non-DT plat
On Monday 14 July 2014 20:44:50 Daniel Lezcano wrote:
> > --- a/drivers/cpuidle/Kconfig.arm
> > +++ b/drivers/cpuidle/Kconfig.arm
> > @@ -10,6 +10,7 @@ config ARM_ARMADA_370_XP_CPUIDLE
> > config ARM_BIG_LITTLE_CPUIDLE
> > bool "Support for ARM big.LITTLE processors"
> > depends on AR
On Mon, Jul 14, 2014 at 2:45 PM, Randy Dunlap wrote:
> On 07/14/14 11:40, Paul Bolle wrote:
>> On Mon, 2014-07-14 at 11:23 -0700, Randy Dunlap wrote:
>>> On 07/14/14 11:14, Nicholas Krause wrote:
This patch addresses the fix me message in this file that states to
remove all definitions n
On Fri, Jul 11, 2014 at 03:45:08PM +0200, Arnd Bergmann wrote:
> The s3c_dma_client structures and the 'ch' and 'ops' members in
> s3c_dma_params were only used by the legacy DMA driver and serve
> no function any more. This removes any reference to them.
Applied, thanks.
signature.asc
Descripti
On Monday 14 July 2014 14:14:24 Nicholas Krause wrote:
> This patch addresses the fix me message in this file that states to
> remove all definitions not related to reg-clocks in this header
> file.
I believe the comment is meant to change the code still using those
definitions so they are no long
On Fri, Jul 11, 2014 at 03:45:07PM +0200, Arnd Bergmann wrote:
> Commit ae602456e83c92 ("ASoC: samsung: drop support for legacy
> S3C24XX DMA API") removed the old code for the samsung specific
> DMA interfaces, now that everybody can use dmaengine.
Applied, thanks.
signature.asc
Description: Di
On Mon, Jul 14, 2014 at 9:47 AM, Doug Anderson wrote:
> Sachin,
>
> On Wed, Jul 9, 2014 at 3:22 AM, Sachin Kamat wrote:
>> Removed outdated configs. Enabled most of the configs used on latest
>> Exynos based platforms. This will provide a reference for users trying
>> to verify and test various f
On 07/14/14 11:40, Paul Bolle wrote:
> On Mon, 2014-07-14 at 11:23 -0700, Randy Dunlap wrote:
>> On 07/14/14 11:14, Nicholas Krause wrote:
>>> This patch addresses the fix me message in this file that states to
>>> remove all definitions not related to reg-clocks in this header
>>> file.
>>>
>>> Si
On 07/14/2014 01:23 PM, Arnd Bergmann wrote:
662322fcb6d ("cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config")
made it possible for the big-little cpuidle driver to run on exynos,
which may or may not include MCPM support at compile time, so we
run into a link error when it is disabled:
drive
On Mon, 2014-07-14 at 11:23 -0700, Randy Dunlap wrote:
> On 07/14/14 11:14, Nicholas Krause wrote:
> > This patch addresses the fix me message in this file that states to
> > remove all definitions not related to reg-clocks in this header
> > file.
> >
> > Signed-off-by: Nicholas Krause
> > ---
>
On 07/14/14 11:14, Nicholas Krause wrote:
> This patch addresses the fix me message in this file that states to
> remove all definitions not related to reg-clocks in this header
> file.
>
> Signed-off-by: Nicholas Krause
> ---
> arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +-
On 07/14/14 11:14, Nicholas Krause wrote:
> This patch addresses the fix me message in this file that states to
> remove all definitions not related to reg-clocks in this header
> file.
>
> Signed-off-by: Nicholas Krause
> ---
> arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +-
This patch addresses the fix me message in this file that states to
remove all definitions not related to reg-clocks in this header
file.
Signed-off-by: Nicholas Krause
---
arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-
On Mon, Jul 14, 2014 at 5:49 AM, Vivek Gautam wrote:
> The host controller by itself may sometimes need to handle PHY
> and/or calibrate some of the PHY settings to get full support out
> of the PHY controller. The PHY core provides a calibration
> funtionality now to do so.
> Therefore, facilitat
On Thu, Jul 03, 2014 at 07:40:17AM +0900, Kukjin Kim wrote:
> This patch removes s5p64x0 related WM8580 because of removing support
> for s5p64x0 SoCs.
Applied, thanks.
signature.asc
Description: Digital signature
On Tue, Jul 01, 2014 at 06:32:27AM +0900, Kukjin Kim wrote:
> This patch removes s5pc100 related codes in
> .
Applied, thanks.
signature.asc
Description: Digital signature
On Mon, Jul 14, 2014 at 11:11:44AM +0530, Naveen Krishna Chatradhi wrote:
> @@ -812,6 +800,10 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
> spi->controller_data = cs;
> }
>
> + /* For the non-DT platforms derive chip selects from controller data */
> + if
Inki,
You have acks, and you have the tested-bys you requested. Can you
please pick this up quickly so that we can have graphics working with
an upstream kernel on chromebooks?
Dave, if Inki keeps dragging his feet like this can you please apply
this series directly? These delays are ridiculous a
Vikas,
On Mon, Jul 14, 2014 at 10:00 AM, Doug Anderson wrote:
> Vikas,
>
> On Sun, Jul 13, 2014 at 11:33 PM, Vikas Sajjan
> wrote:
>> From: Doug Anderson
>>
>> The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
>> being reset across sleep/wake. If we don't set it to anythin
Vikas,
On Sun, Jul 13, 2014 at 11:33 PM, Vikas Sajjan wrote:
> From: Doug Anderson
>
> The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
> being reset across sleep/wake. If we don't set it to anything then
> the TPM will be reset. U-Boot will detect this as invalid
> and wi
Sachin,
On Wed, Jul 9, 2014 at 3:22 AM, Sachin Kamat wrote:
> Removed outdated configs. Enabled most of the configs used on latest
> Exynos based platforms. This will provide a reference for users trying
> to verify and test various features on Exynos based platforms and also
> help in detecting
On Mon, 14 Jul 2014, Arnd Bergmann wrote:
> 662322fcb6d ("cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config")
> made it possible for the big-little cpuidle driver to run on exynos,
> which may or may not include MCPM support at compile time, so we
> run into a link error when it is disabled:
>
Hi Bartlomiej,
On Wed, Jul 9, 2014 at 6:17 PM, Bartlomiej Zolnierkiewicz
wrote:
> This patch series adds support for AFTR idle mode on boards with
> secure firmware enabled and allows EXYNOS cpuidle driver usage on
> Exynos4x12 SoCs.
>
> It has been tested on Trats2 board (using Exynos4412 SoC wi
On 11/07/14 14:00, Tushar Behera wrote:
> @@ -103,17 +140,11 @@ static int exynos_audss_clk_probe(struct
> platform_device *pdev)
> return PTR_ERR(reg_base);
> }
>
> - clk_table = devm_kzalloc(&pdev->dev,
> - sizeof(struct clk *) * EXYNOS_AUDSS
On Thu, Jul 10, 2014 at 5:15 PM, Sylwester Nawrocki
wrote:
> On 08/07/14 11:15, Daniel Drake wrote:
>> Testing on ODROID-U2, v3 is not quite working for me, but v2 of the
>> patch was fine.
>> I boot up, run:
>> # speaker-test -c 2 -t wav
>>
>> As soon as I hear the word "front" I press ctrl+c and
Add MAX98090 audio codec, I2S interface and the sound complex
nodes to enable audio on Odroid-X2/U3 boards.
Signed-off-by: Sylwester Nawrocki
---
This patch depends on the series from Marek [1] adding dt sources
for Odroid X2/U3. My testing branch can be pulled from [2].
[1] http://www.spinics.n
Fix building of exynos_defconfig with CONFIG_PM_SLEEP disabled and
CONFIG_ARM_EXYNOS_CPUIDLE enabled by:
* adding EXYNOS_CPU_SUSPEND config option
* building pm.o and sleep.o if EXYNOS_CPU_SUSPEND is enabled
* moving suspend specific code from pm.c to suspend.c
* enabling pm-common.o build also fo
Fix building of exynos_defconfig with disabled CONFIG_PM_SLEEP by
adding checking whether Exynos cpuidle support is enabled before
accessing exynos_enter_aftr.
The build error message:
arch/arm/mach-exynos/built-in.o:(.data+0x74): undefined reference to
`exynos_enter_aftr'
make: *** [vmlinux] Err
Hi,
This patch series fixes builds with CONFIG_PM_SLEEP config option
disabled.
They are on top of:
- next-20140714 +
- "[PATCH 5/6] ARM: EXYNOS: Fix suspend/resume sequencies" +
(http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg32809.html)
- "[PATCH v2] ARM: EX
From: Thomas Abraham
Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.
Cc: Tomasz Figa
Signed-off-by: Thomas Abraha
On Tue, Jul 8, 2014 at 9:59 AM, Daniel Drake wrote:
> Hi Sean,
>
Hi Daniel,
Sorry for the delay in response.
> While looking at the following commit I noticed something:
>
> commit f041b257a8997c8472a1013e9f252c3e2a1d879e
> Author: Sean Paul
> Date: Thu Jan 30 16:19:15 2014 -0500
>
> drm/
From: Thomas Abraham
Remove the platform device instantiation for exynos cpufreq driver and add the
platform device for generic cpufreq drivers.
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
Acked-by: Viresh Kumar
Reviewed-by: Amit Daniel Kachhap
Tested-by: Arjun K.V
---
arch/arm/mach-exyno
From: Thomas Abraham
Exynos4210 and Exynos5250 based platforms have switched over to use generic
cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq
drivers for these platforms can be removed.
Signed-off-by: Thomas Abraham
Acked-by: Viresh Kumar
Reviewed-by: Amit Daniel K
From: Thomas Abraham
This patch defines a new clock type for CPU clock provider and adds
infrastructure to register the CPU clock providers for Samsung platforms.
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could va
From: Thomas Abraham
For Exynos 4210/5250/5420 based platforms, add CPU nodes, operating points and
cpu clock data for migrating from Exynos specific cpufreq driver to using
generic cpufreq drivers.
Cc: Kukjin Kim
Signed-off-by: Thomas Abraham
Reviewed-by: Amit Daniel Kachhap
Tested-by: Arjun
From: Thomas Abraham
Register cpu clocks using the new cpu-clock provider type for exynos platforms.
The differnt clock blocks that are now encapsulated within the cpu-clock can be
marked with read-only attribute.
Cc: Tomasz Figa
Signed-off-by: Thomas Abraham
Reviewed-by: Amit Daniel Kachhap
Changes since v6:
- Fixes suggested by Amit Daniel .
This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq
drivers and enables the use of cpufreq-cpu0 driver for these platforms. This
series also enabled cpufreq support for Exynos5420 using arm_big_little cpufreq
driver.
On pon, 2014-07-14 at 07:35 -0400, Nicolas Pitre wrote:
> On Mon, 14 Jul 2014, Krzysztof Kozlowski wrote:
>
> > Building of EXYNOS5420_MCPM with disabled SUSPEND fails:
> > arch/arm/mach-exynos/built-in.o: In function `exynos_mcpm_init':
> > arch/arm/mach-exynos/mcpm-exynos.c:361: undefined refere
Some PHY controllers may need to calibrate certain
PHY settings after initialization of the controller and
sometimes even after initializing the PHY-consumer too.
Add support for the same in order to let consumers do so in need.
Signed-off-by: vivek Gautam
---
drivers/phy/phy-core.c | 36
This series is based on Heikki's patches for simpliefied phy lookup table:
[PATCHv2 0/6] phy: simplified phy lookup [1], applied against 'next' branch
of Kishon's linux-phy tree.
Changes since v2:
1) Removed any check for DWC3 in xhci-plat for getting usb2-phy and usb3-phy,
in order to make it
Adding phy calibrate callback, which facilitates setting certain
PHY settings post initialization of the PHY controller.
Exynos5420 and Exynos5800 have 28nm USB 3.0 DRD PHY for which
the Loss-of-Signal (LOS) Detector Threshold Level as well as
Tx-Vboost-Level should be controlled for Super-Speed op
The host controller by itself may sometimes need to handle PHY
and/or calibrate some of the PHY settings to get full support out
of the PHY controller. The PHY core provides a calibration
funtionality now to do so.
Therefore, facilitate getting the two possible PHYs, viz.
USB 2.0 type (UTMI+) and U
Some quirky PHYs may require to be calibrated post the
hcd initialization.
The USB 3.0 DRD PHY on Exynos5420/5800 systems, coming along
with Synopsys's DWC3 controller, is one such PHY which needs
to be calibrated post xhci's reset at initialization time and
at resume time, to get the controller wo
From: Kamil Debski
This patch adds basic support for USB modules (host and device) on
OdroidX board.
Signed-off-by: Kamil Debski
[removed incorrect port@2 node]
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 27 +++
1 file changed, 27 in
Hello,
This is the third version of the initial patch series adding support
for Exynos 4412 based Odroid X2 and U2/U3/U3+ boards and improving
support for Odroid X.
Complete USB support for Odroid U2/U3/U3+ still requires some fixes in
Exynos4 USB2 Phy driver and clock driver for CLKOUT:
http://t
This patch moves some parts of exynos4412-odroidx.dts to common
exynos4412-odroid-common.dtsi file and adds support for Odroid X2 and
U2/U3 boards. X2 is same as X, but it has faster SoC module (1.7GHz
instead of 1.4GHz), while U2/U3 differs from X2 by different way of
routing signals to host USB h
Last megabyte of RAM is used by secure firmware and should not be accessed
by Linux kernel, so correct available memory size in DTS file.
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot
This patch adds support for simple GPIO-based button availabled on
Exynos4 based Odroid boards. All supported boards have POWER button,
which has been defined in exynos4412-odroid-common.dtsi. X/X2 boards
also have additional user-configurable button which has been mapped to
KEY_HOME. All defined k
This patch adds support for common hardware modules available on all
Exynos4412-based Odroid boards, which already have complete support in
mainline kernel. This includes secure firmware calls, watchdog, g2d and
fimc (mem2mem) multimedia accelerators.
Signed-off-by: Marek Szyprowski
---
arch/arm
This patch adds port sub-nodes to exynos4 ehci and ohci modules, which
are required by recently merged new exynos4 usb2 phy support.
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos4.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/
TFLASH (SDHCI2 controller) uses internal card detect line, but it looks
that the driver fails to operate it properly. Use GPIO interrupt on
SD_CDn line for detecting SD card state.
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 2 ++
1 file changed, 2 inser
From: Kamil Debski
On Odroid U2/U3 BUCK8 is used for providing power to also to P3V3
source, which is also connected to LAN9730 chip's nRESET signal. To
reset lan chip on system reboot, the BUCK8 output should not be used in
'always on' mode. This change has no impact on X/X2 boards.
Signed-off-
Hello Vikas,
On 14 July 2014 12:03, Vikas Sajjan wrote:
> From: Doug Anderson
>
> The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
> being reset across sleep/wake. If we don't set it to anything then
> the TPM will be reset. U-Boot will detect this as invalid
> and will r
Hello Vikas,
On 14 July 2014 17:36, Vikas Sajjan wrote:
> The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
> being reset across sleep/wake. If we don't set it to anything then
> the TPM will be reset. U-Boot will detect this as invalid
> and will reset the system on resume
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will
This patch adds a dt-binding include for Maxim 77686
PMIC clock IDs that can be used by both the max77686
clock driver and Device Tree source files.
Signed-off-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
Reviewed-by: Mike Turquette
---
Changes since v6: None
Changes since v5
The MAX77686 RTC chip has two features called SMPL (Sudden Momentary
Power Loss) and WTSR (Watchdog Timeout and Software Resets).
Support for these features seems to be implemented in the driver but
compilation is disabled using a C pre-processor conditional.
This code has been disabled since the
The MAX77802 PMIC has two 32.768kHz Buffered Clock Outputs with
Low Jitter Mode. This patch adds support for these two clocks.
Signed-off-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
---
Changes since v6: None
Changes since v5: None
Changes since v4: None
Changes since v3: N
The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout
(LDO) regulators. This patch adds support for all these regulators
found on the MAX77802 PMIC and is based on a driver added by Simon
Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas
Tested-by: Naveen
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the "#clock-cells" property is
used to specify the number of cells in a clock provider.
But the binding document is not clear enough that it shall
be set to 1 since the PMIC support multiple clocks outputs.
Al
Maxim Integrated Power Management ICs are very similar with
regard to their clock outputs. Most of the clock drivers for
these chips are duplicating code and are simpler enough that
can be converted to use a generic driver to consolidate code
and avoid duplication.
Signed-off-by: Javier Martinez C
Tested-by: Arun Kumar K
on Samsung chromebook boards : Snow, pit and pi.
Regards
Arun
On Wed, Jul 9, 2014 at 3:52 PM, Sachin Kamat wrote:
> Removed outdated configs. Enabled most of the configs used on latest
> Exynos based platforms. This will provide a reference for users trying
> to verify
From: Doug Anderson
The max77686 includes an RTC that keeps power during suspend. It's
convenient to be able to use it as a wakeup source.
NOTE: due to wakeup ordering problems this patch alone doesn't work so
well on exynos5250-snow. You also need something that brings the i2c
bus up before t
Add Device Tree binding documentation for the clocks
outputs in the Maxim 77802 Power Management IC.
Signed-off-by: Javier Martinez Canillas
---
Changes since v6: None
Changes since v5:
- Fix typo error in DT binding. Suggested by Andreas Farber.
- Add "clock-output-names" as an optional prop
This patch set does the following
1: Get fifosize from DT node. But, not mandating it.
2. Corrects the case and default order in a switch
3. Defines a variable to simply the code.
Console messages on Exynos5420 based peach pit and pi works fine.
Naveen Krishna Chatradhi (3):
serial: samsung: ge
The cases should comes before default in a switch.
Even if we want the case and default to share same code.
Its good to define the case first followed by default.
Signed-off-by: Naveen Krishna Chatradhi
Cc: gre...@linuxfoundation.org
---
drivers/tty/serial/samsung.c |2 +-
1 file changed, 1
UART modules on some SoCs only differ in the fifosize of each
UART channel. Its useless to duplicate the drv_data structure
or create a compatible name for such a change.
We can get fifosize via the device tree nodes (not mandating it).
Also updates the documentation.
Signed-off-by: Naveen Krish
The of_node is derived from pdev for every usage, define a
device_node variable instead.
Signed-off-by: Naveen Krishna Chatradhi
Cc: gre...@linuxfoundation.org
---
drivers/tty/serial/samsung.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/sams
The MAX7802 PMIC has a Real-Time-Clock (RTC) with two alarms.
This patch adds support for the RTC and is based on a driver
added by Simon Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
---
Changes since v6:
- Remove unused code
Clocks drivers for Maxim PMIC are very similar so they can
be converted to use the generic Maxim clock driver.
Also, while being there use module_platform_driver() helper
macro to eliminate more boilerplate code.
Signed-off-by: Javier Martinez Canillas
Reviewed-by: Krzysztof Kozlowski
---
driv
Peach pit and pi boards uses a Maxim 77802 power management
IC to drive regulators and its Real Time Clock. This patch
adds support for this chip.
These are the device nodes and pinctrl configuration that
are present on the Peach pit DeviceTree source file in the
the Chrome OS kernel 3.8 tree.
Si
Add Device Tree binding documentation for Maxim 77802 PMIC.
Signed-off-by: Javier Martinez Canillas
---
Changes since v7:
- Remove information about DVS since that will be added as a follow up.
Changes since v6: None
Changes since v5:
- Use max77686,* properties instead of max77802,* since t
Maxim MAX77802 is a power management chip that contains 10 high
efficiency Buck regulators, 32 Low-dropout (LDO) regulators used
to power up application processors and peripherals, a 2-channel
32kHz clock outputs, a Real-Time-Clock (RTC) and a I2C interface
to program the individual regulators, clo
This series are based on drivers added by Simon Glass to the Chrome OS
kernel and adds support for the Maxim 77802 Power Management IC, their
regulators, clocks, RTC and i2c interface.
This is a v8 of the patch-set that addresses issues pointed out in v7.
Individual changes are added on each patch
On Mon, 14 Jul 2014, Krzysztof Kozlowski wrote:
> Building of EXYNOS5420_MCPM with disabled SUSPEND fails:
> arch/arm/mach-exynos/built-in.o: In function `exynos_mcpm_init':
> arch/arm/mach-exynos/mcpm-exynos.c:361: undefined reference to `mcpm_loopback'
>
> The exynos_mcpm_init() in mcp-exynos.c
On Mon, Jul 14, 2014 at 01:27:53PM +0200, Sylwester Nawrocki wrote:
> Too bad, I noticed this comment only just now. I'll consider this and
> will try again and see how simple-card could be used. There is also the
> samsung-i2s-sec secondary 'overlay' CPU DAI that would need to be handled,
> and
On 30/06/14 20:46, Mark Brown wrote:
> On Wed, Jun 18, 2014 at 06:22:30PM +0200, Sylwester Nawrocki wrote:
>
>> +struct odroidx2_drv_data odroidx2_drvdata = {
>> +.dapm_widgets = odroidx2_dapm_widgets,
>> +.num_dapm_widgets = ARRAY_SIZE(odroidx2_dapm_widgets),
>> +};
>> +
>
On Mon, Jul 14, 2014 at 3:38 PM, Sachin Kamat wrote:
> Since the USB 2.0 PHYs are required with EHCI/OHCI USB drivers and
> USB gadget controller supported by the DWC2 gadget driver, make it
> depend on them and default to ARCH_EXYNOS as they are meant for
> Exynos platforms. Also, make the sub-dr
Building of EXYNOS5420_MCPM with disabled SUSPEND fails:
arch/arm/mach-exynos/built-in.o: In function `exynos_mcpm_init':
arch/arm/mach-exynos/mcpm-exynos.c:361: undefined reference to `mcpm_loopback'
The exynos_mcpm_init() in mcp-exynos.c calls mcpm_loopback() which
depends on cpu_suspend functio
662322fcb6d ("cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config")
made it possible for the big-little cpuidle driver to run on exynos,
which may or may not include MCPM support at compile time, so we
run into a link error when it is disabled:
drivers/built-in.o: In function `bl_enter_powerdown'
On Mon, Jul 14, 2014 at 3:38 PM, Sachin Kamat wrote:
> USB DWC3 driver on Exynos platform does not work without its
> corresponding phy driver. Hence make the PHY driver depend on
> Exynos DWC3 driver and default it to yes to make things easier
> for the end user.
>
> Signed-off-by: Sachin Kamat
On Mon, Jul 14, 2014 at 07:45:28PM +0900, YoungJun Cho wrote:
> On 07/14/2014 06:41 PM, Thierry Reding wrote:
[...]
> >That said, I've been doing some research and it seems like we have a
> >somewhat similar feature on Tegra. What happens there is that there are
> >three GPIO pins that can be repur
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